A New Memory Address Transformation for Continuous-Flow FFT Processors with SIMD Extension
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The property of addresses accessed by one butterfly in FFT processors arises the difficulty for parallel accessing during computation. And the address reversal at input or output stage increases the difficulty for parallel I/O. In this paper, a new and simple generalized memory address transformation method supporting parallel accessing for computation is proposed to accelerate 2n-point Mixed-Radix FFT for memory-based FFT processors with SIMD extension. To make I/O clock cycles match up with computation cycles, a new I/O addresses parallel generation method is also proposed. The advantages of the method proposed in this paper lie in the fact that they support the maximum throughput SIMD memory with multi-bank structures and in-place policy for both I/O and computation with continuous data flow. And most importantly, the address transformation circuit for FFT computations is low-complexity with only XOR gates; the I/O addresses parallel generation circuit is also simple with just counters.
KeywordsFFT SIMD Mixed-Radix Memory-based Parallel access Continuous-flow
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