Abstract
Internal thermal problem has become a critical challenge in multi-core 3D ICs. The interlayer cooling system provided a new solution for this problem, and expanded the design space of multi-core microprocessor floorplan. This work proposes a thermal-aware floorplanner for multi-core 3D ICs with interlayer cooling, with iterative algorithm based on simulated annealing method. The results show that the maximal temperature is reduced by 15\(^{\circ }\) C, and the temperature gradient is reduced by 28.4\(^{\circ }\) C compared to the baseline design with 3 active device layers.
W. Guo–The research is supported by National Natural Science Foundation of China with Grant No. 61303066 and 61303069.
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Guo, W., Zhang, M., Li, P., Yao, C., Zhou, H. (2016). Thermal-Aware Floorplanner for Multi-core 3D ICs with Interlayer Cooling. In: Xu, W., Xiao, L., Li, J., Zhang, C. (eds) Computer Engineering and Technology. NCCET 2015. Communications in Computer and Information Science, vol 592. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-49283-3_3
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DOI: https://doi.org/10.1007/978-3-662-49283-3_3
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