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Thermal-Aware Floorplanner for Multi-core 3D ICs with Interlayer Cooling

  • Wei GuoEmail author
  • Minxuan Zhang
  • Peng Li
  • Chaoyun Yao
  • Hongwei Zhou
Conference paper
  • 529 Downloads
Part of the Communications in Computer and Information Science book series (CCIS, volume 592)

Abstract

Internal thermal problem has become a critical challenge in multi-core 3D ICs. The interlayer cooling system provided a new solution for this problem, and expanded the design space of multi-core microprocessor floorplan. This work proposes a thermal-aware floorplanner for multi-core 3D ICs with interlayer cooling, with iterative algorithm based on simulated annealing method. The results show that the maximal temperature is reduced by 15\(^{\circ }\) C, and the temperature gradient is reduced by 28.4\(^{\circ }\) C compared to the baseline design with 3 active device layers.

Keywords

3D ICs Interlayer cooling Floorplan Multi-core Thermal 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2016

Authors and Affiliations

  • Wei Guo
    • 1
    Email author
  • Minxuan Zhang
    • 1
  • Peng Li
    • 1
  • Chaoyun Yao
    • 1
  • Hongwei Zhou
    • 1
  1. 1.College of ComputerNational University of Defense TechnologyChangshaPeople’s Republic of China

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