Abstract
Fast independent component analysis (FastICA) is an efficient and popular algorithm to solve blind source separation (BSS) problems. FastICA is widely used to identify artifact and interference from their mixtures such as electroencephalogram (EEG), magnetoencephalography (MEG), and electrocar-diogram (ECG). In this paper, we propose a Scalable Macro-pipelined FastICA Architecture (SMFA) which aims to exploit architectural scalability and temporal parallelism. The SMFA has strong data processing ability for on-line EEG signals and is capable of coping with different types of input data. The FastICA algorithm based on the proposed SMFA is implemented on a field programmable gate array (FPGA). It’s a key module of an ongoing project which aims to evaluate human’s fatigue degree on-line from EEG. Experimental results demonstrate the effectiveness of the presented FastICA architecture as expected.
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Zhao, D., Jiang, J., Wang, C., Lu, B., Zhu, Y. (2015). FPGA Implementation of FastICA Algorithm for On-line EEG Signal Separation. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2014. Communications in Computer and Information Science, vol 491. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-45815-0_6
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DOI: https://doi.org/10.1007/978-3-662-45815-0_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-662-45814-3
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