Abstract
In this paper, we proposed a novel multicast routing algorithm for the 3D Bufferless Hybrid Interconnection Network to enhance the overall system performance. The proposed algorithm makes use of a single-hop and broadcast (bus-based) interlayer communication of the 3D NoC-Bus mesh architecture. Compared to the DRM_noPR multicast routing algorithm, our simulations with six different synthetic workloads reveal that our architecture using the proposed multicast routing algorithm acquires high system performance.
Keywords
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References
Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Design Automation Conference (DAC 2001), pp. 684–689 (2001)
Carloni, L.P., Pande, P., Xie, Y.: Networks-on-chip in emerging interconnect paradigms: Advantages and challenges. In: Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, pp. 93–102 (2009)
Rahmani, A.-M., Latif, K., Vaddina, K.R., Liljeberg, P., Plosila, J., Tenhunen, H.: Congestion Aware, Fault Tolerant and Thermally Efficient Inter-Layer Communication Scheme for Hybrid NoC-Bus 3D Architectures. In: Proceedings of the 5th ACM/IEEE International Symposium on Networks-on-Chip, pp. 65–72 (2011)
Matsutani, H., Koibuchi, M., Yamada, Y., Hsu, D.F., Amano, H.: Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Transactions on Parallel and Distributed Systems 20(8), 1126–1141 (2009)
Pavlidis, V.F., Friedman, E.G.: 3-D Topologies for Networks-on-Chip. IEEE Transactions on Very Large Scale Integration Systems 15(10), 1081–1090 (2007)
Kim, J., Nicopoulos, C., Park, D., Das, R., Xie, Y., Vijaykrishnan, N., Yousif, M., Das, C.: A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures. In: Proceedings of the International Symposium on Computer Architecture (ISCA 2007), pp. 138–149 (2007)
Li, F., Nicopoulos, C., Richardson, T., Xie, Y., Narayanan, V., Kandemir, M.: Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. In: Proceedings of the International Symposium on Computer Architecture, pp. 130–141 (June 2006)
Ramanujam, R.S., Lin, B.: Randomized Partially-Minimal Routing on Three-Dimensional Mesh Networks. IEEE Computer Architecture Letters 7(2), 37–40 (2008)
Moosavi, S.R., Rahmani, A.M., Liljeberg, P., et al.: Enhancing Performance of 3D Interconnection Networks using Efficient Multicast Communication Protocol. In: 2013 21st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp. 294–301. IEEE (2013)
Rahmani, A.-M., Latif, K., Vaddina, K.R., Liljeberg, P., Plosila, J., Tenhunen, H.: ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures. In: Proceedings of the 17th Asia and South Pacific Design Automation Conference, pp. 413–418 (2012)
Rahmani, A.-M., Vaddina, K.R., Latif, K., Liljeberg, P., Plosila, J., Tenhunen, H.: Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures. In: Proceedings of the 6th ACM/IEEE International Symposium on Networks-on-Chip, pp. 177–184 (2012)
McKinley, P.K., Xu, H., Ni, L.M., Esfahanian, A.H.: Unicast-based multicast communication in wormhole-routed networks. IEEE Trans. Parallel Distrib. 12, 1252–1265 (1994)
Daneshtalab, M., Ebrahimi, M., Mohammadi, S., Afzali-Kusha, A.: Low distance path-based multicast algorithm in NOCs. IET (IEE) -Computers and Digital Techniques, Special issue on NoC 3(5), 430–442 (2009)
Jerger, N.E., Peh, L.-S., Lipasti, M.: Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support. In: Proceedings of the 35th Annual International Symposium on Computer Architecture, pp. 229–240 (2008)
Hu, W., Lu, Z., Jantsch, A., Liu, H.: Power-efficient tree-based multicast support for networks-on-chip. In: Proc. 16th Asia and South Pacific Design Automation Conference, Piscataway, NJ, USA, pp. 363–368 (2011)
Wang, L., Kim, H., Kim, E.J.: Recursive Partitioning Multicast: A Bandwidth-Efficient routing for Networks-On-Chip. In: International Symposium on Networks-on-Chip (NOCS), San Diego, CA (May 2009)
Feero, B., Pratim Pande, P.: Performance Evaluation for Three-Dimensional Networks-on-Chip. In: Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), May 9-11, pp. 305–310 (2007)
Feero, B.S., Pande, P.P.: Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation. IEEE Transactions on Computers 58(1), 32–45 (2009)
Chaochao, F., Zhonghai, L.U., Jantsch, A., et al.: Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip. IEICE Transactions on Information and Systems 95(4), 1052–1061 (2012)
Millberg, M., Nilsson, E., Thid, R., Kumar, S., Jantsch, A.: The nostrum backbone-a communication protocols stack for networks on chip. In: Proc. IEEE Computer Society, Int. Conference on VLSI Design, pp. 693–696 (2004)
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Yao, C., Feng, C., Zhang, M., Wei, S. (2015). Low Latency Multicasting Scheme for Bufferless Hybrid NoC-Bus 3D On-Chip Networks. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2014. Communications in Computer and Information Science, vol 491. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-45815-0_4
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DOI: https://doi.org/10.1007/978-3-662-45815-0_4
Publisher Name: Springer, Berlin, Heidelberg
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