Abstract
With the progress of integrated circuit technology, the soft error problem is getting worse, which has become a challenge that researchers have to face. 3D integration technology can stack several circuit layers in a vertical direction, and 3D chips have an effect of shielding, which is capable of reducing the soft error rate of the inner circuit. In this paper, we propose a dynamic mapping optimization method to reduce the soft error rate of LSQ based on the observation of the characteristics of the LSQ access behavior using 3D integration technology. The experimental result shows that, the proposed method can significantly reduce the soft error rate by 86.6% and 85.7%, on average, for the load queue and store queue respectively.
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Song, C., Zhang, Mx. (2015). Dynamic Mapping Optimization for LSQ Soft Error Rate Reduction under 3D Integration Technology. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2014. Communications in Computer and Information Science, vol 491. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-45815-0_18
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DOI: https://doi.org/10.1007/978-3-662-45815-0_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-662-45814-3
Online ISBN: 978-3-662-45815-0
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