Abstract
This paper proposes a fully pipelined dual-mode double precision floating-point reduction circuit on the field programming gate arrays (FPGAs), which is capable of supporting one double-precision operation and two parallel single-precision operations. Through the combination of tree-traversal structure and striding mode structure, the reduction circuit can handle multiple data sets with arbitrary combination of different lengths without stall and buffer requirements, and generate in-order results. Experimental results show that the proposed reduction circuit can support the dual-mode double precision floating-point reduction at the cost of only 7% increment in the absolute latency for the double precision vector with the same length, compared with the previous single-mode double precision reduction circuits.
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Guo, S., Dou, Y., Lei, Y. (2015). Design of Fully Pipelined Dual-Mode Double Precision Reduction Circuit on FPGAs. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2014. Communications in Computer and Information Science, vol 491. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-45815-0_12
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DOI: https://doi.org/10.1007/978-3-662-45815-0_12
Publisher Name: Springer, Berlin, Heidelberg
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