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Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation

  • Marco GaudesiEmail author
  • Maksim Jenihhin
  • Jaan Raik
  • Ernesto Sanchez
  • Giovanni Squillero
  • Valentin Tihhomirov
  • Raimund Ubar
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8602)

Abstract

Verification is increasingly becoming a bottleneck in the process of designing electronic circuits. While there exists several verification tools that assist in detecting occurrences of design errors, or bugs, there is a lack of solutions for accurately pin-pointing the root causes of these errors. Statistical bug localization has proven to be an approach that scales up to large designs and is widely utilized both in debugging hardware and software. However, the accuracy of localization is highly dependent on the quality of the stimuli. In this paper we formulate diagnostic test set generation as a task for an evolutionary algorithm, and propose dedicated fitness functions that closely correlate with the bug localization capabilities. We perform experiments on the register-transfer level design of the Plasma microprocessor coupling an evolutionary test-pattern generator and a simulator for fitness evaluation. As a result, the diagnostic resolution of the tests is significantly improved.

Keywords

Diagnostic test pattern generation Design error localization Evolutionary computation MicroGP ZamiaCAD 

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References

  1. 1.
    ITRS. International Technology Roadmap for Semiconductors report. URL: http://www.itrs.net/
  2. 2.
    FP6 PROSYD (2004). PROSYD (Property-Based System Design), FP6 funded STREP. http://www.prosyd.org/
  3. 3.
    Peischl, B., Wotawa, F.: Automated Source-Level Error Localization in Hardware Designs. Design&Test of Computers 23(1), 8–19 (2006)Google Scholar
  4. 4.
    Smith, A., Veneris, A., Viglas, A.: Design Diagnosis Using Boolean Satisfiability. In: Proc. Asia and South Pacific Design Automation Conference (ASPDAC), pp. 218–223 (2004)Google Scholar
  5. 5.
    Chang, K.-H., Wagner, I., Bertacco, V., Markov, I.L.: Automatic Error Diagnosis and Correction for RTL Designs. In: Proceedings International Workshop on Logic and Synthesis (IWLS), pp. 106-113 (May 2007)Google Scholar
  6. 6.
    Liblit, B., Naik, M., Zheng, A.X., Aiken, A., Jordan, M.I.: Scalable statistical bug isolation. ACM SIGPLAN Notices 40(6), 15–26 (2005)CrossRefGoogle Scholar
  7. 7.
    Liu, G., Fei, L., Yan, X., Han, J., Midkiff, S.P.: Statistical debugging: A hypothesis testing-based approach. IEEE Trans. on Software Engineering 32(10), 831–848 (2006)CrossRefGoogle Scholar
  8. 8.
    Wong, W.E., Debroy, V., Choi, B.: A family of code coverage-based heuristics for effective fault localization. J. of Systems and Software 83(2), 188–208 (2010)CrossRefGoogle Scholar
  9. 9.
    Cleve, H., Zeller, A.: Locating causes of program failures. In: Proceedings Int. Conf. on Software Engineering, pp. 342-351 (2005)Google Scholar
  10. 10.
    Jones, J.A., Harrold, M.J.: Empirical evaluation of the Tarantula automatic fault-localization technique. In: Int. Conf. on Automated Software Engineering, pp. 273-283 (2005)Google Scholar
  11. 11.
    Tšepurov, A., Tihhomirov, V., Jenihhin, M., Raik, J., Bartsch, G., Meza Escobar, J.H., Wuttke, H.D.: Localization of Bugs in Processor Designs Using zamiaCAD Framework. In: 13th International Workshop on Microprocessor Test and Verification (MTV 2012) Common Challenges and Solutions (2012)Google Scholar
  12. 12.
    Tihhomirov, V., Tšepurov, A., Jenihhin, M., Raik, J., Ubar, R.: Assessment of diagnostic test for automated bug localization. In: 14th Latin American Test Workshop (LATW), p. 6 (2013)Google Scholar
  13. 13.
    Deng, S., Cheng, K.-T., Bian, J., Kong, Z.: Mutation-based diagnostic test generation for hardware design error diagnosis. In: IEEE International Test Conference (ITC) (2010)Google Scholar
  14. 14.
    Bernardi, P., Sánchez, E.E., Schillaci, M., Squillero, G., Sonza Reorda, M.: An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores. IEEE Transactions on CAD of ICs and Systems 27(3), 570-574 (2008)Google Scholar
  15. 15.
    Abreu, R., Zoeteweij, P., van Gemund, A.J.C.: On the Accuracy of Spectrum-based Fault Localization. In: Testing: Academic and Industrial Conference Practice and Research Techniques – MUTATION. TAICPART-MUTATION 2007, pp. 89–98 (2007)Google Scholar
  16. 16.
    Raik, J., Repinski, U.: Comparison of Model-Based Error Localization Algorithms for C Designs. In: Proc. of 10th East-West Design & Test Symposium (2012)Google Scholar
  17. 17.
    Lisherness, P., Cheng, K.-T.: Coverage discounting: A generalized approach for testbench qualification. In: IEEE International High Level Design Validation and Test Workshop (HLDVT), pp. 49-56 (November 9-11, 2011)Google Scholar
  18. 18.
    zamiaCAD framework web page. http://zamiaCAD.sf.net
  19. 19.
    Tšepurov, A., Bartsch, G., Dorsch, R., Jenihhin, M., Raik, J., Tihhomirov, V.: A Scalable Model Based RTL Framework zamiaCAD for Static Analysis. In: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz, USA (2012)Google Scholar
  20. 20.
    Drechsler, R.: Evolutionary Algorithms for VLSI CAD. Springer (1998) ISBN: 978-1-4419-5040-6Google Scholar
  21. 21.
    Squillero, G.: Artificial evolution in computer aided design: from the optimization of parameters to the creation of assembly programs. Computing 93(2-4), 102–120 (2011)CrossRefMathSciNetGoogle Scholar
  22. 22.
    Corno, F., Sonza Reorda, M., Squillero, G.: RT-level ITC’99 benchmarks and first ATPG results. IEEE Design & Test of Computers 17(3), 44–53 (2000)Google Scholar
  23. 23.
    Corno, F., Sanchez, E., Sonza Reorda, M., Squillero, G.: Automatic test generation for verifying microprocessors. IEEE Potentials 24(1), 34–37 (2005)Google Scholar
  24. 24.
    Squillero, G.: MicroGP—An Evolutionary Assembly Program Generator. Genetic Programming and Evolvable Machines 6(3), 247–263 (2005)CrossRefGoogle Scholar
  25. 25.
    Sanchez, E., Schillaci, M., Squillero, G.: Evolutionary Optimization: the µGP toolkit. Springer (2011). ISBN: 978-0-387-09426-7Google Scholar
  26. 26.
    Plasma CPU project. http://opencores.org/project plasma

Copyright information

© Springer-Verlag Berlin Heidelberg 2014

Authors and Affiliations

  • Marco Gaudesi
    • 1
    Email author
  • Maksim Jenihhin
    • 2
  • Jaan Raik
    • 2
  • Ernesto Sanchez
    • 1
  • Giovanni Squillero
    • 1
  • Valentin Tihhomirov
    • 2
  • Raimund Ubar
    • 2
  1. 1.Politecnico di TorinoTorinoITALY
  2. 2.Tallinn University of TechnologyTallinnESTONIA

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