Overcoming Variability Through Transistor Reconfiguration: Evolvable Hardware on the PAnDA Architecture

Abstract

The speed and function density of field-programmable gate arrays (FPGAs) are increasing as transistor sizes shrink to the nano-scale. As transistors reduce in size and approach the atomic scale, the presence or absence of single doping atoms and structural irregularities are likely to affect the behaviour of the device in a random manner (Papanikolaou et al, 2006). Despite advances in the manufacturing process, the fundamentally granular nature of matter can not be overcome and the impact will increase as the technology continues to shrink further (Asenov, 2007; Nassif et al, 2007; Takeuchi et al, 2007). As intrinsic variability becomes more of a problem, every physical instance of a design will behave differently, which will result in a decrease in fabrication yield.