Hierarchical Networks-on-Chip Architecture for Neuromorphic Hardware

Abstract

The mammalian brain has become one of the most interesting and active research topics, not only for neuroscientists, but also for computer scientists and engineers. However, whilst neuroscientists are interested in biophysical models (Trappenberg, 2009), computer scientists and engineers are more interested in the brain’s powerful signal-processing capability (Paugam-Moisy and Bohte, 2012), which is able to perform extraordinary computational feats such as highly parallel, low-powered, fault tolerant computing in comparison to traditional computer paradigms, i.e. generalpurpose computers, which have a centralised sequential hardware architecture based on the von Neumann computing approach (Patterson et al, 2006).