Abstract
A novel memory consistency model for thousand-core processors is presented. The model simplifies cache coherence for the full chip, and reduces cache design complexity. In addition, the model has the ability to describe the direct exchange of data on chip, thereby alleviating the off-chip memory bandwidth requirements. The paper gives a formal definition of the model, and proves that the model is sequentially consistent. All aspects of the definition are fully used in the process of proof, which means that there is no redundancy in the definition. Therefore, based on the split-range shared memory consistency model, a shared memory system can achieve high performance at low hardware cost. Meanwhile, the model is easy to be understood and used by programmers.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Tile-gx100 manycore processor: acceleration interfaces and architecture, http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.18.2-security/HC23.18.220-TILE-GX100-Ramey-Tilera-e.pdf (accessed May 15, 2014)
Johnson, D.R., Johnson, M.R., Kelm, J.H.: Rigel: A 1,024-core single-chip accelerator architecture. IEEE Micro 31, 30–41 (2011)
Lamport, L.: How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers 28, 690–691(1979)
Owens, S., Sarkar, S., Sewell, P.: A better x86 memory model: x86-TSO. In: Berghofer, S., Nipkow, T., Urban, C., Wenzel, M. (eds.) TPHOLs 2009. LNCS, vol. 5674, pp. 391–407. Springer, Heidelberg (2009)
Weaver, D.L., Germond, T.: The SPARC architecture manual (Version 9). PTR Prentice Hall, Englewood Cliffs (1994)
Hechtman, B.A., Sorin, D.J.: Exploring memory consistency for massively-threaded throughput-oriented processors. In: Proc. of the 40th Annual International Symposium on Computer Architecture, pp. 201–212. ACM, New York (2013)
Kelm, J.H., Johnson, M.R., Lumettta, S.S.: Waypoint: Scaling coherence to thousand-core architectures. In: Proc. of the 19th International Conference on Parallel Architectures and Compilation Techniques, pp. 99–110. ACM, New York (2010)
Hower, D.: Acoherent shared memory. University of Wisconsin-Madison, Madison (2012)
Kelm, J.H., Johnson, D.R., Tuohy, W.: Cohesion: An adaptive hybrid memory model for accelerators. IEEE Micro 31, 42–55 (2011)
Kelm, J.H., Johnson, D.R., Lumetta, S.S.: A Task-Centric Memory Model for Scalable Accelerator Architectures. IEEE Micro 30, 29–39 (2010)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lyu, H., Zheng, F., Xie, X. (2014). SRS: A Split-Range Shared Memory Consistency Model for Thousand-Core Processors. In: Wu, J., Chen, H., Wang, X. (eds) Advanced Computer Architecture. Communications in Computer and Information Science, vol 451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-44491-7_3
Download citation
DOI: https://doi.org/10.1007/978-3-662-44491-7_3
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-662-44490-0
Online ISBN: 978-3-662-44491-7
eBook Packages: Computer ScienceComputer Science (R0)