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A Novel Design of Flexible Crypto Coprocessor and Its Application

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Advanced Computer Architecture

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 451))

Abstract

Accelerating security protocols has been a great challenge in general-purpose processor due to the complexity of crypto algorithms. Most crypto algorithms are employed at the function level among different security protocols. We propose a novel flexible crypto coprocessor architecture that relies on Reconfigurable Cryptographic Blocks (RCBs) to achieve a balance between high performance and flexibility and implement the architecture for security application on FPGA. The pipelining technique is adopted to realize parallel data and to reduce the commication costs. We consider several crypto algorithms as examples to illustrate the design of the RCB in the FC Coprocessor. Finally, we create a prototype of the FC coprocessor on a Xilinx XC5VLX330 FPGA chip. The experiment results show that the coprocessor, running at 216 MHz, outperforms the software-based file encryption running on an Intel Core i3 530 CPU at 2.93 GHz by a factor of 29× for typical encrypt application.

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References

  1. Freier, A.O., Karlton, P., Kocher, P.C.: Introduction to SSL. IETF draft (1996), https://developer.mozilla.org/zh-CN/docs/Introduction_to_SSL#The_SSL_Protocol

  2. Kent, S., Atkinson, R.: Security Architecture for the Internet Protocol. RFC 2401 (November 1998)

    Google Scholar 

  3. Taylor, R.R., Goldstein, S.C.: A High-Performance Flexible Architecture for Cryptography. In: Koç, Ç.K., Paar, C. (eds.) CHES 1999. LNCS, vol. 1717, pp. 231–245. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  4. Antão, S., Chaves, R., Sousa, L.: AES and ECC Cryptography Processor with Runtime Configuration. In: Proceedings of ADCOM (2009)

    Google Scholar 

  5. Hodjat, A., Verbauwhede, I.: A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA. In: Proc. FCCM 2004 (2004)

    Google Scholar 

  6. Mazzeo, A., Romano, L., Saggese, G.P., et al.: FPGA-based Implementation of a serial RSA processor. In: Proc. DATE 2003 (2003)

    Google Scholar 

  7. Michail, H.E., Athanasios, P., et al.: Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores. IEEE Transactions on Dependable and Secure Computing 6(4), 255–268 (2009)

    Article  Google Scholar 

  8. Kakarountas, A.P., Michail, H.: High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications. The Journal of Supercomputing 37, 179–195 (2006)

    Article  Google Scholar 

  9. Elbirt, A.J., Paar, C.: An Instruction-Level Distributed Processor for Symmetric-Key Cryptography. IEEE Transactions on Parallel and Distributed Systems 16(5) (2005)

    Google Scholar 

  10. Mosanya, E., Teuscher, C., Restrepo, H.F., Galley, P., Sánchez, E.: CryptoBooster: A Reconfigurable and Modular Cryptographic Coprocessor. In: Koç, Ç.K., Paar, C. (eds.) CHES 1999. LNCS, vol. 1717, pp. 246–256. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  11. Prasanna, V.K., Dandalis, A.: FPGA-based Cryptography for Internet Security. In: Online Symposium for Electronic Engineers (2000)

    Google Scholar 

  12. Li, M., Ji, X., Liu, B.: Analysing and Researching Montgomery Algorithm. Science Technology and Engineering 6, 1628–1631 (2006)

    Google Scholar 

  13. Rivest, R.L.: The MD5 Message-Digest Algorithm. RFC 1321, MIT Laboratory for Computer Science and RSA Data Security, Inc. (April 1992)

    Google Scholar 

  14. Rivest, R., Shamir, A., Adleman, L.: A Method for Obtaining Digital Signatures and Public-Key Cryptosystems. Communications of the ACM 21, 120–126 (1978)

    Article  MATH  MathSciNet  Google Scholar 

  15. NIST Federal Information Processing Standards Publication, FIPS PUB 180-2 (2002)

    Google Scholar 

  16. National Institute of Standards and Technology. Advanced Encryption Standard (AES). Federal Information Processing Standards Publications – FIPS 197 (2001)

    Google Scholar 

  17. FIPS PUB 46-3, Data Encryption Standard (DES), Reaffirmed (1977)

    Google Scholar 

  18. Rivest, R.L.: The RC5 Encryption Algorithm. In: Preneel, B. (ed.) FSE 1994. LNCS, vol. 1008, pp. 86–96. Springer, Heidelberg (1995)

    Chapter  Google Scholar 

  19. OProfile. OProfile Website (2012), http://oprofile.sourceforge.net/news/

  20. Bouhraous, A.: Design feasibility study for a 500Gbits/s advanced encryption standard cipher/decipher engine. IET Computers & Digital Techniques 4(4), 334–348 (2010)

    Article  Google Scholar 

  21. Kwok, S.H.M., Lam, E.Y.: Effective Uses of FPGAs for Brute-Force Attack on RC4 Ciphers. IEEE Transactions on VLSI Systems 16(8) (August 2008)

    Google Scholar 

  22. Michail, H.E., et al.: On the Exploitation of a High-Throughput SHA-256 FPGA Design for HMACACM. Transactions on Reconfigurable Technology and Systems 5(1) (2012)

    Google Scholar 

  23. Wang, Y., Zhao, Q., Jiang, L., Shao, Y.: Ultra-High Throughput Implementations for MD5 Hash Algorithm on FPGA. In: Zhang, W., Chen, Z., Douglas, C.C., Tong, W. (eds.) HPCA 2009. LNCS, vol. 5938, pp. 433–441. Springer, Heidelberg (2010)

    Chapter  Google Scholar 

  24. Blum, T., Paar, C.: High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware. IEEE Transaction on Computer 50(7) (2001)

    Google Scholar 

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Ni, S., Dou, Y., Chen, K., Deng, L. (2014). A Novel Design of Flexible Crypto Coprocessor and Its Application. In: Wu, J., Chen, H., Wang, X. (eds) Advanced Computer Architecture. Communications in Computer and Information Science, vol 451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-44491-7_10

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  • DOI: https://doi.org/10.1007/978-3-662-44491-7_10

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-662-44490-0

  • Online ISBN: 978-3-662-44491-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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