Abstract
Two comparators in 65 nm low-power CMOS are introduced in this chapter. First a high-speed comparator for a sample rate of 7 GHz inclusive measured results is presented. The second comparator is optimized with respect to a low offset voltage, but nevertheless achieves a maximum clock frequency of 5 GHz.
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B. Goll, H. Zimmermann, A 65nm CMOS comparator with modified latch to achieve 7 GHz/1.3 mW at 1.2 V and 700 MHz/47 \(\mu \)W at 0.6 V, in IEEE International Solid-State Circuits Conference, pp. 328–329 (2009)
D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, B. Nauta, A double-tail latch-type voltage sense amplifier with 18 ps setup-hold time, in IEEE International Solid-State Circuits Conference, pp. 314–315 (2007)
B. Goll, H. Zimmermann, A comparator with reduced delay time in 65-nm CMOS for Supply voltages down to 0.65 V. IEEE Trans. Circuits Syst-II: Express Briefs 56(11), 810–814 (2009)
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Goll, B., Zimmermann, H. (2015). Comparators in 65 nm CMOS. In: Comparators in Nanometer CMOS Technology. Springer Series in Advanced Microelectronics, vol 50. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-44482-5_7
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DOI: https://doi.org/10.1007/978-3-662-44482-5_7
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