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Comparators in 65 nm CMOS

  • Bernhard GollEmail author
  • Horst Zimmermann
Chapter
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 50)

Abstract

Two comparators in 65 nm low-power CMOS are introduced in this chapter. First a high-speed comparator for a sample rate of 7 GHz inclusive measured results is presented. The second comparator is optimized with respect to a low offset voltage, but nevertheless achieves a maximum clock frequency of 5 GHz.

Keywords

Supply Voltage Clock Frequency Microstrip Line Test Board Test Chip 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    B. Goll, H. Zimmermann, A 65nm CMOS comparator with modified latch to achieve 7 GHz/1.3 mW at 1.2 V and 700 MHz/47 \(\mu \)W at 0.6 V, in IEEE International Solid-State Circuits Conference, pp. 328–329 (2009)Google Scholar
  2. 2.
    D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, B. Nauta, A double-tail latch-type voltage sense amplifier with 18 ps setup-hold time, in IEEE International Solid-State Circuits Conference, pp. 314–315 (2007)Google Scholar
  3. 3.
    B. Goll, H. Zimmermann, A comparator with reduced delay time in 65-nm CMOS for Supply voltages down to 0.65 V. IEEE Trans. Circuits Syst-II: Express Briefs 56(11), 810–814 (2009)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  1. 1.Institute of Electrodynamics, Microwave and Circuit Engineering (EMCE)TU WienWienAustria

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