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Nanometer CMOS Technology

  • Bernhard GollEmail author
  • Horst Zimmermann
Chapter
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 50)

Abstract

In this chapter the CMOS technologies used for design and fabrication of comparator test chips described in this book are introduced. The MOS transistor characteristics in nanometer CMOS are shown.

Keywords

Analog Circuit Gate Length NMOS Transistor PMOS Transistor Gate Leakage Current 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    H. De Man, From the Heaven of Software to the Hell of Nanoscale Physics: An Industry in Transition (Keynote Slides, ACACES, 2007)Google Scholar
  2. 2.
    C11N Design Manual, Infineon/ALTIS, confidentialGoogle Scholar
  3. 3.
    F. Schlögl, Fully Differential Operational Amplifiers in Deep-Sub-\(\mu \)m CMOS Technology, Ph.D. thesis, Vienna University of Technology (2004), pp. 11–15Google Scholar
  4. 4.
    K. Schneider, Burst-Mode Receivers for Passive Optical Networks, Ph.D. thesis, Vienna University of Technology (2004), pp. 18–21Google Scholar
  5. 5.
    K. Schneider, H. Zimmermann, Highly Sensitive Optical Receiver (Springer, Berlin, 2006)CrossRefGoogle Scholar
  6. 6.
    P.R. Gray, P.J. Hurst, S.H. Lews, R.G. Meyer, Analysis and Design of Analog Integrated Circuits (Wiley, New York, 2001)Google Scholar
  7. 7.
    P. Andreani, S. Mattissson, On the use of MOS varactors in RF VCOs. IEEE J. Solid-State Circuits 35(6), 905–910 (2000)CrossRefGoogle Scholar
  8. 8.
    Z. Luo, A. Steegen, M. Eller, R. Mann, C. Baiocco, P. Nguyen, L. Kim, M. Hoinkis, V. Ku, V. Klee, F. Jamin, P. Wrschka, P. Shafer, W. Lin, S. Fang, A. Ajmera, W. Tan, D. Park, R. Mo, J. Lian, D. Vietzke, C. Coppock, A. Vayshenker, T. Hook, V. Chan, K. Kim, A. Cowley, S. Kim, E. Kaltalioglu, B. Zhang, S. Marokkey, Y. Lin, K. Lee, H. Zhu, M. Weybright, R. Rengarajan, J. Ku, T. Schiml, J. Sudijono, I. Yang, C. Wann, High performance and low power transistors integrated in 65 nm bulk CMOS technology. IEEE International Electron Devices Meeting, 2004, pp. 661–664Google Scholar
  9. 9.
    S. Maeda, Y-S. Jin, J-A. Choi, S-Y. Oh, H-W. Lee, J-Y. Yoo, M-C. Sun, J-H. Ku, K. Lee, S-G. Bae, S-G. Kang, J-H. Yang, Y-W. Kim, K-P. Suh, Impact of mechanical stress engineering on Flicker noise characteristics. Symposium on VLSI technology, June 2004, pp. 102–103Google Scholar
  10. 10.
    B. Tavel, M. Bidaud, N. Emonet, D. Barge, N. Planes, H. Brut, D. Roy, J.C. Vildeuil, R. Difrenza, K. Rochereau, M. Denais, V. Huard, P. Llinares, S. Bruyere, C. Parthasarthy, N. Revil, R. Pantel, F. Guyader, L. Vishnubotla, K. Barla, F. Arnaud, P. Stolk, M. Woo, Thin oxynitride solution for digital and mixed-signal 65 nm CMOS platform. IEEE International Electron Devices Meeting, 2003, pp. 643–646Google Scholar
  11. 11.
    P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S.-H. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, M. Bohr, A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, Low-k ILD and 0.57 \(\upmu \text{ m }^2\) SRAM cell. IEEE International Electron Devices Meeting, 2004, pp. 657–660Google Scholar
  12. 12.
    F. Ji, J.P. Xu, J.J. Chen, H.X. Xu, C.X. Li, P.T. Lai, A compact threshold-voltage model of MOSFETs with stack high-k gate dielectric. IEEE International Conference of Electron Devices and Solid-State Circuits, 2009, pp, 236–239Google Scholar
  13. 13.
    A. Mercha, W. Jeamsaksiri, J. Ramos, S. Jenei, S. Decoutere, D. Linten, P. Wambacq, Impact of scaling on analog/RF CMOS performance. IEEE Solid-State and Integrated Circuits Technology, Oct 2004, pp. 147–152Google Scholar
  14. 14.
    A.-J. Annema, B. Nauta, R. van Langevelde, H. Tuinhout, Analog circuits in ultra-deep-submicron CMOS. IEEE J. Solid-State Circuits 40(1), 132–143 (2005)CrossRefGoogle Scholar
  15. 15.
    J.-H. Lee, S.-Y. Kim, I. Cho, S. Hwang, J.-H. Lee, 1/f Noise characteristics of sub-100 nm MOS transistors. J. Semicond. Technol. Sci. 6(1), 38–42 (2006)Google Scholar
  16. 16.
    W.M.C. Sansen, Analog Design Essentials (Springer, New York, 2006)Google Scholar
  17. 17.
    L. Lanny, L. Trond Ytterdal, C. Wulff, K. Martin, Analog circuit design in nanoscale CMOS technologies. Proc. of the IEEE 97(10), 1687–1714 (2009)Google Scholar
  18. 18.
    R. van Langevelde, L.F. Tiemeijer, R.J. Havens, M.J. Knitel, R.F.M. Roes, P.H. Woerlee, D.B.M. Klaassen, RF-distortion in deep-submicron CMOS technologies. IEEE International Electron Devices Meeting, 2000, pp. 807–810Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  1. 1.Institute of Electrodynamics, Microwave and Circuit Engineering (EMCE)TU WienWienAustria

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