Parallel Associative Combinator Evaluation

  • Martin Waite
  • Bret Giddings
  • Simon Lavington
Part of the Lecture Notes in Computer Science book series (LNCS, volume 506)

Abstract

A new evaluation model for SK combinator expressions is presented and used as a basis for the design of a novel processor. The resulting machine architecture resembles a dataflow ring, but executions are constrained to be fully lazy. When used in a multiprocessor context, different grains of parallelism are exploited at different architectural levels. A dynamic load sharing mechanism based on the current physical state of the machine is suggested. Initial simulation results are presented, and the cost-effectiveness of the proposed architecture is discussed.

Keywords

Europe Coherence Nises Bret Amico 

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Copyright information

© Springer-Verlag Berlin Heidelberg 1991

Authors and Affiliations

  • Martin Waite
    • 1
  • Bret Giddings
    • 1
  • Simon Lavington
    • 1
  1. 1.Department of Computer ScienceUniversity of EssexColchester, EssexEngland

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