Parallel Associative Combinator Evaluation

  • Martin Waite
  • Bret Giddings
  • Simon Lavington
Part of the Lecture Notes in Computer Science book series (LNCS, volume 506)


A new evaluation model for SK combinator expressions is presented and used as a basis for the design of a novel processor. The resulting machine architecture resembles a dataflow ring, but executions are constrained to be fully lazy. When used in a multiprocessor context, different grains of parallelism are exploited at different architectural levels. A dynamic load sharing mechanism based on the current physical state of the machine is suggested. Initial simulation results are presented, and the cost-effectiveness of the proposed architecture is discussed.


Europe Coherence Nises Bret Amico 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [ArN87]
    Arvind and R.S. Nikhil, “Executing a program on the tagged-token dataflow architecture”, Proc. PARLE (Parallel Languages and Architectures, Europe) Conference, Eindhoven. LNCS Springer Verlag, 1987.Google Scholar
  2. [ArI87]
    Arvind and R.A. Ianucci, “Two Fundamental Issues in Multiprocessing”, CSG Memo 226–6, Lab for Computer Science, MIT, 1987.Google Scholar
  3. [AuJ90]
    L. Augustsson and T. Johnsson, Version 0.99 of LML Department of Computer Science, Chalmers University of Technology, Gothenburg, 1990.Google Scholar
  4. [Bev89]
    D.J. Bevan, G.L. Burn, R.J. Karia and J.D. Robson, “Principles for the Design of a Distributed Memory Architecture for Parallel Graph Reduction”, The Computer Journal, Vol 32 No 5, 1989.Google Scholar
  5. [C1a80]
    T.J. Clarke, P.J.S. Gladstone, C.D. MacLean and A.C. Norman, “SKIM - the S K I reduction machine”, Proc. ACM Lisp Conference, Stanford CA, 1980.Google Scholar
  6. [HaV88]
    P.H. Hartel and A.H. Veen, “Statistics on Graph Reduction of SASL Programs”, Software–Practice and Experience Vol 18 (3), 239–253, March 1988.CrossRefGoogle Scholar
  7. [Hea90]
    M.J. Heaton, “Pacetool: A Monitoring Tool for PACE”, Department of Computer Science, University of Essex, September 1990.Google Scholar
  8. [Hug83]
    J. Hughes, “The Design and Implementation of Programming Languages”, PhD. Thesis,Oxford University (1983). (Published as Oxford University Computing Laboratory, Programming Research Group, Technical Monograph PRG-40, September 1984.)Google Scholar
  9. [NoP88]
    E. Nocker and R. Plasmeyer, “Combinator Reduction on a Parallel G-Machine”, in Parallel Processing and Applications, E.Chiricozzi and A.D’Amico (eds), ( North-Holland ), 1988, 399–412Google Scholar
  10. [Pey87]
    S. Peyton-Jones, C. Clack, J. Salkild and M. Hardie, “GRIP: A high performance architecture for parallel graph reduction”, Functional Programming Languages and Computer Architecture, ed Kahn, Portland, Oregon. LNCS 274 Springer Verlag, 1987.Google Scholar
  11. [Pey89]
    S. Peyton-Jones, “Parallel Implementations of Functional Programming Languages”, The Computer Journal, Vol 32, No 2, 1989.Google Scholar
  12. [Joh84]
    T. Johnsson, “Efficient Compilation of Lazy Evaluation”, Proc. ACM SIGPLAN ‘84, Symposium on Compiler Construction, SIGPLAN Notice, Vol 19, No 6, June 1984.Google Scholar
  13. [Sch86]
    M. Scheevel, “NORMA — a graph reduction processor”, Proc. ACM Conference on Lisp and Functional Programming, Aug 1986.Google Scholar
  14. [Tur79]
    D.A. Turner, “A New Implementation Technique for Applicative Languages”, Software — Practice and Experience, Vol 9, 31–49, 1979.CrossRefMATHGoogle Scholar
  15. [Wat85]
    I. Watson, P. Watson and V. Woods, “Parallel Data-Driven Graph Reduction”, University of Manchester, 1985.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1991

Authors and Affiliations

  • Martin Waite
    • 1
  • Bret Giddings
    • 1
  • Simon Lavington
    • 1
  1. 1.Department of Computer ScienceUniversity of EssexColchester, EssexEngland

Personalised recommendations