Skip to main content

Mapping Uniform Recurrences onto Small Size Arrays

  • Conference paper
Parle ’91 Parallel Architectures and Languages Europe

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 505))

  • 706 Accesses

Abstract

Given a regular application described by a system of uniform recurrence equations, systolic arrays are commonly derived by means of an affine transformation; an affine schedule determines when the computations are performed and an affine processor allocation where they are performed. Circuit transformations are then applied on the resulting circuit when the application needs to be mapped onto a smaller size array. This method is in two steps and thus can hardly be optimized globally.

We hereafter present a different method for designing small size arrays. We derive them in one step by means of an affine schedule and a near-affine processor allocation. By doing so, we can generalize the optimization technique for affine mapping to be applicable here. The method is illustrated on the band-matrix multiplication and on the convolution algorithms.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. M. Annaratone, E. Arnould, T. Gross, H.T. Kung, M. Lam, O. Menzilcioglu, and J.A. Webb. The warp computer: architecture, implementation, and performance. IEEE Trans. on Computers, 36 (12): 1523–1538, December 1987.

    Article  Google Scholar 

  2. H. Brams. Adaptation du logiciel Presage à la génération de réseaux systoliques implémentables sur un réseau de Transputers. Technical Report RR 90–23, Université Catholique de Louvain, Novembre 1990.

    Google Scholar 

  3. J. Bu. Systematic Design of Regular VLSI Processor Arrays. PhD thesis, Delft University of Technology, May 1990.

    Google Scholar 

  4. P. Clauss. Synthèse d’Algorithmes Systoliques et Implantation Optimale en Place sur Réseaux de Processeurs Synchrones. PhD thesis, Université de Franche-Comté, 1990.

    Google Scholar 

  5. J.-M. Delosme and I.C.F. Ipsen. Sage and condense: a two-phase approach for the implementation of recurrence equations on multiprocessors architectures. In L.W. Hoevel, editor, 21st Annual Hawai Int. Conf. on System Sciences, pages 126–130, 1988.

    Google Scholar 

  6. M. Garcia and J. Navarro. Systematic hardware adaptation of systolic algorithms. In IEEE, editor, The 16th Annual Int. Symp. on Comp. Architecture, pages 96–104, Computer Society Press, 1989.

    Google Scholar 

  7. H.T. Kung and C.E. Leiserson. Systolic arrays (for VLSI). In Sparse Matrix Proc. 1978, pages 256–282, Society for Industrial and Applied Mathematics, 1978.

    Google Scholar 

  8. R.M. Karp, R.E. Miller, and S. Winograd. The organization of computations for uniform recurrence equations. Journal of the ACM, 1967.

    Google Scholar 

  9. S.Y. Kung. VLSI array processors. Signal and Image Processing Institute, 1987.

    Google Scholar 

  10. C. Mead and L. Conway. Introduction to VLSI Systems, chapter 8, Highly Concurrent Systems, pages 263–332. Addison-Wesley Series in Computer Science, 1980.

    Google Scholar 

  11. D.I. Moldovan. On the design of algorithms for VLSI systolic arrays. IEEE Proceedings, 1983.

    Google Scholar 

  12. H. Neils and E. Deprettere. Automatic design and partitioning of systolic/wavefront arrays for visi. Circuits Systems and Signal Processing, Vol. 7 (2): 235–252, 1988.

    Article  Google Scholar 

  13. P. Quinton. Automatic synthesis of systolic arrays from uniform recurrent equations. In Proc. IEEE 11-th Int. Sym. on Computer Architecture, 1984.

    Google Scholar 

  14. S.K. Rao. Regular iterative algorithms and their implementations on processor arrays. PhD thesis, Information Systems lab., Standford University, 1985.

    Google Scholar 

  15. The transputer databook. 2nd ed. Inmos, Bristol, 1989.

    Google Scholar 

  16. V. Van Dongen. From Systolic to Periodic Array Design. PhD thesis, Université Catholique de Louvain, January 1991.

    Google Scholar 

  17. V. Van Dongen and M. Petit. Presage: a tool for the parallelization of nested loop programs. In L. Claesen (ed.), editor, Formal VLSI Specification and Synthesis (VLSI Design Methods-I), pages 341–359, North-Holland, 1990.

    Google Scholar 

  18. Y. Wong and J.M. Delosme. Optimal systolic implementations of n-dimensional recurrences. In IEEE Int. Conf. on Computer Design: VLSI in Computers, pages 618–621, Oct. 7–10 1985.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1991 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Van Dongen, V. (1991). Mapping Uniform Recurrences onto Small Size Arrays. In: Aarts, E.H.L., van Leeuwen, J., Rem, M. (eds) Parle ’91 Parallel Architectures and Languages Europe. Lecture Notes in Computer Science, vol 505. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-25209-3_14

Download citation

  • DOI: https://doi.org/10.1007/978-3-662-25209-3_14

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-662-23206-4

  • Online ISBN: 978-3-662-25209-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics