Advertisement

Wafer Bonding pp 193-261 | Cite as

Application of Bonded Wafers to the Fabrication of Electronic Devices

  • A. W. Nevin
Chapter
Part of the Springer Series in MATERIALS SCIENCE book series (SSMATERIALS, volume 75)

Abstract

This chapter reviews the application of wafer bonding to the fabrication of electronic devices, with the main focus on silicon-on-insulator (SOI) substrates prepared by fusion bonding of silicon-related materials. Since several comprehensive reviews have recently been published on the use of thin (thickness < 1 µm) SOI material for low-power, low-voltage, high-speed VLSI CMOS, such as for DRAMs [22, 64, 140], the chapter will concentrate on relatively thick-film bonded SOI, in the range of 1–2 µm and above. Initially, the application of standard SOI will be described, with particular emphasis on the fabrication of trench-isolated structures and the performance benefits gained through the utilisation of this technology for both low- and high-voltage products. Subsequent sections will cover more novel processing, such as the incorporation of silicide buried layers and the combination of integrated microelectronics with sensing or actuating elements fabricated on the same substrate. Finally, applications related to direct silicon-onsilicon bonding, where the buried oxide (BOX) is eliminated, will be described.

Keywords

Breakdown Voltage Bipolar Transistor Minority Carrier Lifetime Wafer Bonding Silicide Layer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Abe T, Sunakawa K, Hagimoto K, Aga K (1995) The behavior of grown-in defects during the wafer bonding process. In: Hunt CE, Baumgart H, Iyer SS, Abe T, Gösele U (eds) Semiconductor wafer bonding: physics and applications III. Electrochem Soc, Pennington, PV 95–7, pp 296–304Google Scholar
  2. 2.
    Amaratunga GAJ, Udrea F, McMahon RA (1999) Power integrated circuits: devices and applications. In: Proc 1999 bipolar circuits and technology meeting. IEEE, pp 7579Google Scholar
  3. 3.
    Amirfeiz P, Bengtsson S, Bergh M, Zanghellini E, Börjesson L (2000) Formation of silicon structures by plasma-activated wafer bonding. J Electrochem Soc 147: 26932698Google Scholar
  4. 4.
    Armstrong GA, Gamble HS (1999) Simulation of self heating effects in heterojunction bipolar transistors fabricated in wafer bonded SOI substrates. In: Hemment PLF (ed) Silicon-on-insulator technology and devices IX. Electrochem Soc, Pennington, PV 993, pp 249–254Google Scholar
  5. 5.
    Arnold E (1994) Silicon-on-insulator devices for high voltage and power IC applications. J Electrochem Soc 141: 1983–1988CrossRefGoogle Scholar
  6. 6.
    Ashburn P, El Mubarek HAW, Bonar JM, Redman-White W (2001) SiGe heterojunction bipolar transistors on insulator. In: Cristoloveanu S, Hemment PLF, Izumi K, Cel1er GK, Assaderaghi F, Kim Y-W (eds) Silicon-on-insulator technology and devices X. Electrochem Soc, Pennington, PV 2001–3, pp 433–444Google Scholar
  7. 7.
    Aspar B, Auberton-Hery•AJ (2002) Smart Cut: the technology used for high volume SOI wafer production. In: Iyer SS, Auberton-HeryI’SS (eds) Silicon wafer bonding technology for VLSI and MEMS applications. Institution of Electrical Engineers, London, pp 35–51Google Scholar
  8. 8.
    Bain MF, Armstrong BM, Gamble HS (2000) The deposition and characterisation of CVD tungsten silicide for applications in microelectronics. Vacuum 64: 227–232CrossRefGoogle Scholar
  9. 9.
    Baliga BJ (1995) Power ICs in the saddle. IEEE Spectrum July: 34–49Google Scholar
  10. 10.
    Bansal IK, Goodrich JP (2002) A manufacturing process for silicon-on-silicon wafer bonding. In: Iyer SS, Auberton-Hery•AJ (eds) Silicon wafer bonding technology for VLSI and MEMS applications. IEE, London, pp 123–134Google Scholar
  11. 11.
    Baumgart H, Letavic TJ, De Wolf I, Tsou L, Maes HE, Egloff R (1995) Analysis of process-induced stresses in lateral trench isolation structures for high voltage devices in bonded SOI. In: Hunt CE, Baumgart H, lyer SS, Abe T, Gösele U (eds) Semiconductor wafer bonding: physics and applications III. Electrochem Soc, Pennington, PV 95–7, pp 440–454Google Scholar
  12. 12.
    Benamara M, Rocher A, Laporte A, Sarrabayrouse G, Lescouzères L, PeyreLavigne A, Fnaiech M, Claverie A (1995) Atomic structure of the interfaces between silicon directly bonded wafers. In: Ashok S, Chevallier J, Akasaki, Johnson NM, Sopo BL (eds) MRS Proc 378: 863–868Google Scholar
  13. 13.
    Bengtsson S, Engström 0 (1990) Low-temperature preparation of silicon/silicon interfaces by the silicon-to-silicon direct bonding method. J Electrochem Soc 137: 2297 2303Google Scholar
  14. 14.
    Blackstone S (1995) Mechanical thinning for SOI. In: Hunt CE, Baumgart H, Iyer SS, Abe T, Gösele U (eds) Semiconductor wafer bonding: physics and applications III. Electrochem Soc, Pennington, PV 95–7, pp 56–71Google Scholar
  15. 15.
    Blackstone S (1997) Silicided buried layers for IC applications. In: Nayar V, Uren M, Ward MC (eds) Tech digest of novel SOI materials and applications workshop IEEE. New York, NY, USA. pp 24–25Google Scholar
  16. 16.
    Blackstone S, Brosnihan T (2001) SOI MEMS technologies for optical switching. In: Proc int conf on optical MEMS. IEEE/LEOS, 35–36Google Scholar
  17. 17.
    Brown A, O’Neill G, Blackstone S (2000) Single-crystal micromachining using multiple fusion bonded layers. In: Micromachining and microfabrication process technology VI. Proc SPIE 4174: 406–415Google Scholar
  18. 18.
    Cao X, Nicholson D, Nevin WA, Knopke J (2001) Control of crystalline defects in trench isolated thick film SOI for high voltage smart power ICs. In: Kolbesen BO, Claeys C, Stallhofer P, Tardif F (eds) Crystalline defects and contamination: their impact and control in device manufacturing III. Electrochem Soc, Pennington, PV 200129, pp 103–111Google Scholar
  19. 19.
    Carline RT, Hope DA, Nayar V, Robbins DJ, Stanaway MB (1997) A vertical cavity longwave infrared SiGe/Si photodetector using a buried silicide mirror. In: IEDM Technical Digest. IEEE, pp 891–894Google Scholar
  20. 20.
    Cha G, Kim Y, Jang H, Kang H, Song C (2001) Silicon direct bonding approach to high-voltage power devices (insulated gate bipolar transistors). In: Tong Q-Y, Gösele U (eds) Advances in microelectronics device technology. Porc SPIE 4600: 88–95Google Scholar
  21. 21.
    Cole D, MacNamara C, Somasundram K, Boyle A, Devine C, McKeever J, McCann P, Nevin A (2002) Fusion-bonded multilayered SOI for MEMS applications. In: Optoelectronics, photonics and imaging. Proc SPIE 4876: 623–632Google Scholar
  22. 22.
    Colinge J-P (1997) Silicon-on-insulator technology: materials to VLSI, 2nd edn. Kluwer, Boston Dordrecht LondonGoogle Scholar
  23. 23.
    Cowen CS, Craven DR, Goodwin CA, Hsieh C-M, Jones GT, Pandhumsoporn T (1996) Deep trench isolation in bonded wafer SOI ICs using high-density ICP etcher. In: Hemment PLF, Cristoloveanu S, Izumi K, Houston T, Wilson S (eds) Silicon-oninsulator technology and devices VII. Electrochem Soc, Pennington, PV 96–3, pp 364373Google Scholar
  24. 24.
    Davis C, Bajor G, Butler J, Crandell T, Delgado J, Jung T, Khajeh-Noori Y, Lomenick B, Milam V, Nicolay H, Richmond S, Rivoli T (1992) UHF-1: A high speed complementary bipolar analog process on SOI. In: Proc 1992 bipolar circuits and technology meeting. IEEE, pp 260–263Google Scholar
  25. 25.
    Desmond CA, Hobart K, Kub F, Campisi G, Weldon M (1998) Low-temperature atmospheric silicon-silicon wafer bonding for power electronic applications. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 459–465Google Scholar
  26. 26.
    Easter WG, Jones GT, Shanaman RH, Goodwin CA (1992) Polysilicon to silicon bonding in laminated dielectrically isolated (LDI) wafers. In: Gösele U, Abe T, Haisma J, Schmidt M (eds) Semiconductor wafer bonding: science, technology and applications. Electrochem Soc, Pennington, PV 92–7, pp 223–229Google Scholar
  27. 27.
    Engström O, Bengtsson S, Andersson GI, Andersson MO, Jauhiainen A (1992) Electrical characterization of bonding interfaces. J Electrochem Soc 139: 3638–3644CrossRefGoogle Scholar
  28. 28.
    Esser R, Hobart KD, Kub FJ (2002) Improved low-temperature hydrophobic Si—Si bonding techniques. In: Baumgart H, Hunt CE, Bengtsson S, Abe T (eds) Semiconductor wafer bonding: science, technology and applications VI. Electrochem Soc, Pennington, PV 2001–27, pp 126–135Google Scholar
  29. 29.
    Farrens S (1998) Low-temperature wafer bonding. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 425–436Google Scholar
  30. 30.
    Farrens SN, Dekker JR, Smith JK, Roberds BE (1995) Chemical free room temperature wafer to wafer direct bonding. J Electrochem Soc 142: 3949–3955CrossRefGoogle Scholar
  31. 31.
    Feindt S, Hajjar J-JJ, Lapham J, Buss D (1992) XFCB: a high speed complementary bipolar process on bonded SOI. In: Proc 1992 bipolar circuits and technology meeting. IEEE, pp 264–267Google Scholar
  32. 32.
    Feindt S, Lapham J, Steigerwald J (1997) Complementary bipolar processes on bonded SOI. In: Proc 1997 Int SOI Conf IEEE, pp 4–6Google Scholar
  33. 33.
    Feindt S, Lapham J, Steigerwald J, Nakazato Y. Katayama M (1998) Bonded SOI application to high-performance linear devices. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 529–535Google Scholar
  34. 34.
    Fujino S, Takahashi S, Fukada T, Himi H, Kawamoto K (2002) Device applications using bonded thick SOI wafers. In: Baumgart H, Hunt CE, Bengtsson S, Abe T (eds) Semiconductor wafer bonding: science, technology and applications VI. Electrochem Soc, Pennington, PV 2001–27, pp 214–231Google Scholar
  35. 35.
    Funaki H, Yamaguchi Y, Kawaguchi Y, Terazaki Y, Mochizuki H, Nakagawa A (1995) High voltage BiCDMOS technology on bonded 2 µm SOI integrating vertical npn pnp, 60 V-LDMOS and MPU, capable of 200°C operation. In: IEDM Tech Digest IEEE, pp 967–970Google Scholar
  36. 36.
    Gamble HS (2001) Variants on bonded SOI for advanced ICs. In: Cristoloveanu S, Hemment PLF, Izumi K, Celler GK, Assaderaghi F, Kim Y-W (eds) Silicon-oninsulator technology and devices X. Electrochem Soc, Pennington, PV 2001–3, pp 112Google Scholar
  37. 37.
    Gamble HS, Armstrong BM, Baine P, Bain M, McNeill DW (2001) Silicon-oninsulator substrates with buried tungsten silicide. Solid-State Electronics 45: 551–557.ADSCrossRefGoogle Scholar
  38. 38.
    Ganci PR, Hajjar J-JJ, Clark T, Humphries P, Lapham J, Buss D (1992) Self-heating in high-performance bipolar transistors fabricated on SOI substrates. In: IEDM Technical Digest. IEEE, pp 417–420Google Scholar
  39. 39.
    Garner DM, Udrea F, Ensell G, Sheng K, Popescu AE, Amaratunga GAJ, Milne WI (2001) Failure mechanisms of SOI high-voltage LIGBTs and LDMOSes under un-clamped inductive switching. In: Proc 13th int Sympos on power semiconductor devices and ICs. IEEE, pp 335–338Google Scholar
  40. 40.
    Goh WL, Campbell DL, Armstrong BM, Gamble HS (1995) Buried metallic layers with silicon direct bonding. In: Hunt CE, Baumgart H, Iyer SS, Abe T, Gösele U (eds) Semiconductor wafer bonding: physics and applications III. Electrochem Soc, Pennington, PV 95–7, pp 553–560Google Scholar
  41. 41.
    Goh WL, Montgomery JH, Raza SH, Armstrong BM, Gamble HS (1997) Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers. IEEE Electron Dev Lett 18: 232–234ADSCrossRefGoogle Scholar
  42. 42.
    Goh WL, Raza SH, Montgomery JH, Armstrong BM, Gamble HS (1999) The manufacture and performance of diodes made in dielectrically isolated silicon substrates containing buried metallic layers. IEEE Electron Dev Lett 20: 212–214ADSCrossRefGoogle Scholar
  43. 43.
    Gonzalez F, Shekhar V, Chan C-K, Choy B, Chen N (1996) Fabrication of a 300 V, high current (300 mA/output), smart power IC using gate-controlled SCRs on bonded (BSOI) technology. In: IEDM Technical Digest. IEEE, pp 473–476Google Scholar
  44. 44.
    Goody SB, Osborne PH, Quinn C, Blackstone S (1998) High speed bipolar on bonded buried silicide SOI (S20I). In: 28th European Solid State Device Research Conf. IEEEGoogle Scholar
  45. 45.
    Gormley C, Yallup K, Nevin WA, Bhardwaj J, Ashraf H, Huggett P, Blackstone S (2001) State of the art deep silicon anisotropic etching on SOI bonded substrates for dielectric isolation and MEMS applications. In: Hunt CE, Baumgart H, Gösele U, Abe T (eds) Semiconductor wafer bonding: science, technology and applications V. Electrochem Soc, Pennington, PV 99–35, pp 350–361Google Scholar
  46. 46.
    Gösele U, Tong Q-Y (1998) Semiconductor wafer bonding. Annu Rev Mater Sci 28: 215–241ADSCrossRefGoogle Scholar
  47. 47.
    Gösele U, Stenzel H, Martini T, Steinkirchner J, Conrad D, Scheerschmidt K (1995) Self-propagating room-temperature silicon wafer bonding in ultrahigh vacuum. Appl Phys Lett 67: 3614–3616ADSCrossRefGoogle Scholar
  48. 48.
    Hamel JS, Stefanou S, Bain M, Armstrong BM, Gamble HS (2000) Substrate crosstalk suppression capability of silicon-on-insulator substrates with buried ground planes ( GPSOI ). IEEE Microwave and Guided Wave Lett 10: 134–135Google Scholar
  49. 49.
    Harendt C, Beintner J, Schuhbauer A, Apel U, Dudek V, Graf H-G, Höfflinger B, Seger U (1998) Photodiodes in bonded SOI films. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 568–575Google Scholar
  50. 50.
    Harendt C, Schuhbauer A, Apel U, Dudek V, Graf H-G, Höfflinger B, Penteker E (1998) Vertical polysilicon interconnects by aligned wafer bonding. In: Gösele U, Baumgart H, Abe T, Hunt C, lyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 501–508Google Scholar
  51. 51.
    Heinle U, Olsson J (2001) Integration of high voltage devices on thick SOI substrates for automotive applications. Solid-State Electronics 45: 629–632ADSCrossRefGoogle Scholar
  52. 52.
    Heinle U, Pinardi K, Olsson J (2002) Vertical high-voltage devices on thick SOI with back-end trench formation. In: Proc 32nd ESSDERC. Univ Bologna, pp 295–298Google Scholar
  53. 53.
    Hermansson K, Frey F, Bengtsson S, Södervall U (1998) Ultra-clean Si/Si interface formation by surface preparation and direct bonding in ultra-high vacuum. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 401–408Google Scholar
  54. 54.
    Hiller E, Stolze D, Wiedand M, Dragoi V, Reiche M (2002) Wafer bonding for optical microsystems. In: Baumgart H, Hunt CE, Bengtsson S, Abe T (eds) Semiconductor wafer bonding: science, technology and applications VI. Electrochem Soc, Pennington, PV 2001–27, pp 254–264Google Scholar
  55. 55.
    Hiramoto T, Tamba N, Yoshida M, Hashimoto T, Fujiwara T, Watanabe K, Odaka M, Usami M, Ikeda T (1992) A 27 GHz double polysilicon bipolar technology on bonded SOI with embedded 58 1.1m2 CMOS memory cells for ECL-CMOS SRAM applications. In: IEDM Technical Digest. IEEE, pp 39–42Google Scholar
  56. 56.
    Hobart KD, Desmond CA, Kub FJ, Twigg ME, Jernigan GG (1998) Si—Si pn junctions fabricated by wafer bonding in UHV. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 409–416Google Scholar
  57. 57.
    Hobart KD, Kub FJ, Dolny G, Zafrani M, Neilson JM, Gladish J, McLachlan C (1999) Fabrication of a double-side IGBT by very low temperature wafer bonding In: Proc 11th int Sympos on power semiconductor devices and ICs. IEEE, pp 45–48Google Scholar
  58. 58.
    Hobart KD, Kub FJ, Ancona M, Neilson JM, Brandmier K, Waind PR (2001) Characterization of a bi-directional double-side double-gate IGBT fabricated by wafer bonding. In: Proc 13th int Sympos on power semiconductor devices and ICs. IEEE, pp 125128Google Scholar
  59. 59.
    Hobart KD, Kub FJ, Pattanayak D, Piccone D, Patel M, Hits D, Rodrigues R, Ayele G, Colinge CA (2001) A 6 kV thyristor fabricated by direct wafer bonding. In: Proc 13th int Sympos on power semiconductor devices and ICs. IEEE, pp 211–214Google Scholar
  60. 60.
    lida M, Nishizawa T, Mizuno S, Kohno K, Higuchi Y, Toyoshima S (1998) Intelligent power ICs on bonded silicon wafers. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 481–492Google Scholar
  61. 61.
    Ikeda T, Watanabe K, Yamaguchi H, Nishizawa H, Tamba N, Usami M, Natsuaki N (1995) High performance bipolar SOI technology. In: Hunt CE, Baumgart H, Iyer SS, Abe T, Gösele U (eds) Semiconductor wafer bonding: physics and applications III. Electrochem Soc, Pennington, PV 95–7, pp 390–399Google Scholar
  62. 62.
    Irissou P, Pilloud V, Yallup K, Brown A, Gaston G, Blackstone S (2001) Complementary bipolar fabricated by the bonding of patterned buried layers. In: Hunt CE, Baumgart H, Gösele U, Abe T (eds) Semiconductor wafer bonding: science, technology and applications V. Electrochem Soc, Pennington, PV 99–35, pp 438–442Google Scholar
  63. 63.
    Johansson M, Bengtsson S (2001) Depleted semi-insulating silicon/silicon material formed by wafer bonding. In: Baumgart H, Hunt CE, Bengtsson S, Abe T (eds) Semiconductor wafer bonding: science, technology and applications VI. Electrochem Soc, Pennington, PV 2001–27, pp 420–428Google Scholar
  64. 64.
    Jones EC, Bedell SW (2002) Advanced applications of wafer bonding. In: Iyer SS, Auberton-Herv•AJ (eds) Silicon wafer bonding technology for VLSI and MEMS applications. Institution of Electrical Engineers, London, pp 93–121CrossRefGoogle Scholar
  65. 65.
    Juneau T, Chen T, Brosnihan T, Rajaraman S, Chau K, Judy M (2003) Single-chip 1x84 MEMS mirror array for optical telecommunications applications. In: Smith JH (ed) MOEMS and Miniaturized Systems III. Proc SPIE 4983: 53–64Google Scholar
  66. 66.
    Kim TH, Yun CM, Kim SS, Jang HW (1999) Characterization of silicon direct bonding methodology for high performance IGBT. In: Proc 11th int Sympos on power semiconductor devices and ICs. IEEE, pp 185–188Google Scholar
  67. 67.
    Kim JH, Lee SH, Lee KH, Park HJ, Cha G, Kang HS, Song CS (2002) A high performance complementary bipolar process using PBSOI technique. In: Proc 14th int Sympos on power semiconductor devices and ICs. IEEE, pp 85–88Google Scholar
  68. 68.
    Kobayashi K, Hamajima T, Kikuchi H, Takahashi M, Kitano T (1997) Application of partially bonded SOI structure to an intelligent power device having vertical DMOSFET. In: Proc 9th int Sympos on power semiconductor devices and ICs. IEEE, pp 309–312Google Scholar
  69. 69.
    Kub FJ, Hobart KD, Desmond CA (1998) Electrical characteristics of low-temperature direct silicon—silicon bonding for power device applications. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 466–472Google Scholar
  70. 70.
    Laporte A, Sarrabayrouse G, Lescouzères L, PeyreLavigne A, Benamara M, Rocher A, Claverie A (1994) Influence of the mechanical conditions on the electrical and structural properties of the interface between bonded silicon wafers. In: Proc 6th int Sympos on power semiconductor devices and ICs. IEEE, pp 293–296Google Scholar
  71. 71.
    Laporte A, Benamara M, Sarrabayrouse G, Rocher A, Lescouzères L, PeyreLavigne A, Claverie A (1995) Misorientation induced defects at silicon bonding interfaces: structural and electrical investigations. In: Hunt CE, Baumgart H, Iyer SS, Abe T, Gösele U (eds) Semiconductor wafer bonding: physics and applications III. Electrochem Soc, Pennington, PV 95–7, pp 342–352Google Scholar
  72. 72.
    Lee MR, Kwon O-K, Lee SS, Lee IH, Yang IS, Paek JH, Hwang LY, Ju JI, Lee BH, Lee C (1999) SOI high-voltage integral circuit technology for plasma display panel drivers. In: Proc 11th int Sympos on power semiconductor devices and ICs. IEEE, pp 285–288Google Scholar
  73. 73.
    Letavic T, Arnold E, Simpson M, Aquino R, Bhimnathwala H, Egloff R, Emmerik S, Wong S, Mukherjee S (1997) High performance 600 V smart power technology based on thin layer silicon-on-insulator. In: Proc 9th int Sympos on power semiconductor devices and ICs. IEEE, pp 49–52Google Scholar
  74. 74.
    Letavic T, Simpson M, Arnold E, Peters E, Aquino R, Curcio J, Herko S, Mukherjee S (1999) 600 V power conversion system-on-a-chip based on thin layer silicon-oninsulator. In: Proc 11th int Sympos on power semiconductor devices and ICs. IEEE, pp 325–328Google Scholar
  75. 75.
    Letavic T, Albu B, Dufort J, Petruzzello M, Simpson M, Mukherjee S (2002) Thin layer silicon-on-insulator high-voltage PMOS device and application. In: Proc 14th int Sympos on power semiconductor devices and ICs. IEEE, pp 73–76Google Scholar
  76. 76.
    Lizotte S, Cantarini W, Quinn C, Nevin A, Blackstone S, Gamble H (1997) Silicided buried layer smart power process. In: Abstract of ECS 192nd meeting. Electrochem Soc, Pennington, pp 2470–2471Google Scholar
  77. 77.
    Ljungberg K, Söderbärg A, Bengtsson S, Jauhiainen A (1994) Characterization of spontaneously bonded hydrophobic silicon surfaces. J Electrochem Soc 141: 562–566CrossRefGoogle Scholar
  78. 78.
    Ljundberg K, Söderbärg A, Tiensuu A-L, Johansson S, Thungström G, Petersson CS (1994) Buried cobalt silicide layers in silicon created by wafer bonding. J Electrochem Soc 141: 2829–2833CrossRefGoogle Scholar
  79. 79.
    Ljungberg K, Bäcklund Y, Söderbärg A, Bergh M, Andersson MO, Bengtsson S (1995) The effects of HF cleaning prior to silicon wafer bonding. J Electrochem Soc 142: 1297–1303CrossRefGoogle Scholar
  80. 80.
    McCann P, Nevin WA (2002) Development and characterization of a silicon-onsilicon fusion-bonded production process. In: Bengtsson S (ed) Tech Digest 2nd Workshop on Wafer BondingGoogle Scholar
  81. 81.
    McCann P, Somasundram K, Byrne S, Nevin A (2001) Conformal deposition of LPCVD TEOS. In: Karam JM, Yasaitis J (eds) Micromachining and microfabrication process technology VII. Proc SPIE 4557: 329–340Google Scholar
  82. 82.
    McCann P, Byrne S, Nevin WA (2002) An investigation into interfacial oxide in direct silicon bonding. In: Baumgart H, Hunt CE, Bengtsson S, Abe T (eds) Semiconductor wafer bonding: science, technology and applications VI. Electrochem Soc, Pennington, PV 2001–27, pp 106–113Google Scholar
  83. 83.
    McCann P, McKeever J, Nicholson D, Ruddell F, Gamble HS, Nevin WA (2002) Electrical and structural characterization of silicon on silicon bonded interfaces. In: Claeys CL, Watanabe M, Rai-Choudhury P, Stallhofer P (eds) High purity silicon VII. Electrochem Soc, Pennington, PV 2002–20, pp 369–376Google Scholar
  84. 84.
    McCann P, Devine C, Gamble HS, Nevin WA (2003) Characteristics and applications of silicon direct bonded interfaces. In: Semiconductor wafer bonding: science, technology and applications VII. Electrochem Soc, Pennington, PV 2003Google Scholar
  85. 85.
    McMullan A J, O’Mahoney D, Nevin W A, Gregg J M, Paxton A T (2003) Study of dislocations and stress in silicon-on-insulator tubs using transmission electron microscopy and finite element modelling. In: Semiconductor wafer bonding: science, technology and applications VII. Electrochem Soc, Pennington, PV 2003Google Scholar
  86. 86.
    Mc Stay K, Smoot F, Hariton D, Egan K, Irvine D, Brown G, Edwards P, Blackstone S, Gamble H (1995) A commodity analog process based on bonded wafers. In: Hunt CE, Baumgart H, Iyer SS, Abe T, Gösele U (eds) Semiconductor wafer bonding: physics and applications III. Electrochem Soc, Pennington, PV 95–7, pp 466–470Google Scholar
  87. 87.
    Merchant S, Arnold E, Baumgart H, Mukherjee S, Pein H, Pinker R (1991) Realization of high breakdown voltages (>700 V) in thin SOI devices. In: Proc 3rd int Sympos on power semiconductor devices and ICs. IEEE, pp 31–35Google Scholar
  88. 88.
    Merchant S, Efland T, Haynie S, Headen W, Kengo K, Paiva S, Shaw R, Tachikake I, Tani T, Tsai C-Y (2002) Robust 80 V LDMOS and 100 V DECMOS in a streamlined SOI technology for analog power applications. In: Proc 14th int Sympos on power semiconductor devices and ICs. IEEE, pp 185–188Google Scholar
  89. 89.
    Meynants G, Poortmans J, Mertens R, Jones S, Polce N, Blackstone S (1998) Excess carrier lifetime and surface recombination velocity in dielectrically isolated Si tubs. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 257–263Google Scholar
  90. 90.
    Mitani K (1998) Silicon wafer bonding: an overview. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 1–12Google Scholar
  91. 91.
    Nakagawa A (1996) Recent advances in high voltage SOI technology for motor control and automotive applications. In: Proc bipolar/BiCMOS circuits and technology meeting. IEEE, pp 69–72Google Scholar
  92. 92.
    Nakagawa A, Watanabe K, Yamaguchi Y, Ohashi H, Furukawa K (1986) 1800 V bipolar-mode MOSFETs: a first application of silicon wafer direct bonding (SBD) technique to a power device. In: IEDM Technical Digest. IEEE, pp 122–125Google Scholar
  93. 93.
    Nakagawa A, Yamaguchi Y, Matsudai T, Yasuhara N (1993) 200°C high-temperature and high-speed operation of 440 V lateral IGBTs on 1.5 µm thick SOI. In: IEDM Technical Digest. IEEE, pp 687–690Google Scholar
  94. 94.
    Nakagawa A, Yamaguchi Y, Yasuhara N, Hirayama K, Funaki H (1996) New high-voltage SOI device structure eliminating substrate bias effects. In: IEDM Technical Digest. IEEE, pp 477–480Google Scholar
  95. 95.
    Nakamura T, Nishizawa H (1995) Recent progress in bipolar transistor technology. IEEE Trans Electron Devices 42: 390–398ADSCrossRefGoogle Scholar
  96. 96.
    Nakamura T, Shiba T, Ikeda T (1996) Bipolar and BiCMOS on SOI. In: Hemment PLF, Cristoloveanu S, Izumi K, Houston T, Wilson S (eds) Silicon-on-insulator technology and devices VII. Electrochem Soc, Pennington, PV 96–3, pp 414–421Google Scholar
  97. 97.
    Nayar V, Carline RT, Newey J, Pidduck AJ, Reeves C, Russell J, Williams G, Quinn C, Nevin A, Blackstone S (1998) Bonded silicon silicide on insulator (S20I) a study of chemical, physical and optical properties for advanced device fabrication. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 544–551Google Scholar
  98. 98.
    Nayar V, Russell J, Carline RT, Pidduck AJ, Quinn C, Nevin A, Blackstone S (1998) Optical properties of bonded silicon silicide on insulator (S2Ol): a new substrate for electronic and optical devices. Thin Solid Films 313–314: 276–280CrossRefGoogle Scholar
  99. 99.
    Nevin WA, Gay DL, O’Neill G (2000) Influence of cleaning on the quality of the bonding interface in direct bonded silicon wafers. Solid State Phenomena 76–77: 173–176Google Scholar
  100. 100.
    Nevin WA, Gay DL, Blackstone S, Higgs V (2001) Photoluminescence study of interface defects in bonded silicon wafers. In: Hunt CE, Baumgart H, Gösele U, Abe T (eds) Semiconductor wafer bonding: science, technology and applications V. Electrochem Soc, Pennington, PV 99–35, pp 187–194Google Scholar
  101. 101.
    Nevin WA, Somasundram K, McCann P, Magee S, Paxton AT (2001) Material effects on stress-induced defect generation in trenched silicon-on-insulator structures. J Electrochem Soc 148: G649 — G654CrossRefGoogle Scholar
  102. 102.
    Nevin WA, Somasundram K, McCann P, Cao X, Byrne S (2002) Factors affecting stress-induced defect generation in trenched SOI for high-voltage applications. In: Baumgart H, Hunt CE, Bengtsson S, Abe T (eds) Semiconductor wafer bonding: science, technology and applications VI. Electrochem Soc, Pennington, PV 2001–27, pp 232–241Google Scholar
  103. 103.
    Ng R, Udrea F, Sheng K, Ueno K, Amaratunga GAJ, Nishiura M (2001) Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI. In: Proc 13th int Sympos on power semiconductor devices and ICs. IEEE, pp 395–398Google Scholar
  104. 104.
    Ohashi H, Ohura J, Tsukakoshi T, Simbo M (1986) Improved dielectrically isolated device integration by silicon-wafer direct bonding (SDB) technique. In: IEDM Technical Digest. IEEE, pp 210–213Google Scholar
  105. 105.
    Ohashi H, Furukawa K, Atsuta M, Nakagawa A, Imamura K (1987) Study of Si-wafer directly bonded interface effect on power device characteristics. In: IEDM Technical Digest. IEEE, pp 678–681Google Scholar
  106. 106.
    Okada C, Kawai Y, Morita E, Saitoh Y (1995) Characterization of the direct bonding of silicon wafers after treatment in dilute HF solution. In: Hunt CE, Baumgart H, Iyer SS, Abe T, Gösele U (eds) Semiconductor wafer bonding: physics and applications III. Electrochem Soc, Pennington, PV 95–7, pp 363–370Google Scholar
  107. 107.
    Okonogi K, Kikuchi H, Arai K (1995) Oxygen precipitate distribution in bonded SOI wafers. In: Hunt CE, Baumgart H, Iyer SS, Abe T, Gösele U (eds) Semiconductor wafer bonding: physics and applications III. Electrochem Soc, Pennington, PV 95–7, pp 290–295Google Scholar
  108. 108.
    Papakonstantinou P, Somasundram K, Cao X, Nevin WA (2001) Crystal surface defects and oxygen gettering in thermally oxidised bonded SOI wafers. J Electrochem Soc 148: G36 — G42CrossRefGoogle Scholar
  109. 109.
    Peidous IV, Loiko KV, Balasubramanian N, Schuelke T (2000) Threshold stresses of dislocation generation onset in silicon. In: Claeys CL, Rai-Choudhury P, Watanabe M Stallhofer P, Dawson HJ (eds) High purity silicon VI. Electrochem Soc, Pennington, PV 2000–17, pp 180–188Google Scholar
  110. 110.
    Plößl A, Scholz R, Schulze H-J, Hopfe S (2001) Bonding of hydrogen-terminated silicon: thermal evolution of the interfacial properties. In: Hunt CE, Baumgart H, Gösele U, Abe T (eds) Semiconductor wafer bonding: science, technology and applications V. Electrochem Soc, Pennington, PV 99–35, pp 224–231Google Scholar
  111. 111.
    Polce N, Calley M, Jones S, Blackstone S, Martin P (2001) HVIC process on bonded wafers with internal gettering. In: Hunt CE, Baumgart H, Gösele U, Abe T (eds) Semiconductor wafer bonding: science, technology and applications V. Electrochem Soc, Pennington, PV 99–35, pp 470–472Google Scholar
  112. 112.
    Reiche M, Gösele U, Tong Q-Y (1994) Interfacial structure of bonded silicon wafers. In: Huff HR, Bergholz W, Sumino K (eds) Semiconductor silicon VII. Electrochem Soc, Pennington, PV 94–10, pp 408–419Google Scholar
  113. 113.
    Reiche M, Gutjahr K, Stolz D, Burczyk D, Petzold M (1998) The effect of a plasma pretreatment on the Si/Si bonding behaviour. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 437–444Google Scholar
  114. 114.
    Reiche M, Wiegand M, Dragoi V (2001) Plasma activation for low-temperature wafer direct bonding. In: Hunt CE, Baumgart H, Gösele U, Abe T (eds) Semiconductor wafer bonding: science, technology and applications V. Electrochem Soc, Pennington, PV 99–35, pp 292–301Google Scholar
  115. 115.
    Reiche M, Hiller E, Stolze D (2002) New substrates for MOEMS. In: Proc IEEE Sensors 2002, vol 1, pp 607–612Google Scholar
  116. 116.
    Reznicek A, Senz S, Breitenstein O, Scholz R, Gösele U (2002) Electrical and structural investigation of bonded silicon interfaces. In: Baumgart H, Hunt CE, Bengtsson S, Abe T (eds) Semiconductor wafer bonding: science, technology and applications VI. Electrochem Soc, Pennington, PV 2001–27, pp 114–125Google Scholar
  117. 117.
    Sanz-Velasco A, Amirfeiz P, Bengtsson S, Colinge C (2002) Wafer bonding using oxygen plasma treatment in RIE and ICP RIE. In: Baumgart H, Hunt CE, Bengtsson S, Abe T (eds) Semiconductor wafer bonding: science, technology and applications VI. Electrochem Soc, Pennington, PV 2001–27, pp 31–40Google Scholar
  118. 118.
    Sato F, Hashimoto T, Tezuka H, Soda M, Suzaki T, Tatsumi T, Tashiro T (1999) A 60—GHz f T super self-aligned selectively grown SiGe-base (SSSB) bipolar transistor with trench isolation fabricated on SOI substrate and its application to 20—Gb/s optical transmitter ICs. IEEE Trans Electron Devices 46: 1332–1338ADSCrossRefGoogle Scholar
  119. 119.
    Saul PH, Goody SB (1996) Bipolar-SOI active filters for UHF radio communications. In: Proc bipolar/BiCMOS circuits and technol meeting. IEEE, pp 161–164Google Scholar
  120. 120.
    Scheerschmidt K, Conrad D, Belov A, Stenzel H (1998) UHV-silicon wafer bonding at room temperature: molecular dynamics and experiments. In: Gösele U, Baumgart H, Abe T, Hunt C, Iyer S (eds) Semiconductor wafer bonding: science, technology and applications IV. Electrochem Soc, Pennington, PV 97–36, pp 381–392Google Scholar
  121. 121.
    Schenk H, Min- P, Haase T, Kunze D, Soe U, Lakner H, Kick H (2000) Large deflection micromechanical scanning mirrors for linear scans and pattern generation. IEEE J Sel Top Quantum Electron 6: 715–722Google Scholar
  122. 122.
    Senz S, Reznicek A, Akatsu T, Kästner G, Scholz R, Gösele U (2002) UHV-bonding: electrical characterization of interfaces and application to magnetoelectronics. In: Baumgart H, Hunt CE, Bengtsson S, Abe T (eds) Semiconductor wafer bonding: science, technology and applications VI. Electrochem Soc, Pennington, PV 2001–27, pp 48–61Google Scholar
  123. 123.
    Sinclair P, Whitney W, Taggart W, Yallup K, Blackstone S (2001) Form C opto-solid state relay on bonded wafer with 1600 V isolation. In: Hunt CE, Baumgart H, Gösele U, Abe T (eds) Semiconductor wafer bonding: science, technology and applications V. Electrochem Soc, Pennington, PV 99–35, pp 402–406Google Scholar
  124. 124.
    Stefanou S, Hamel JS, Bain M, Baine P, Armstrong BM, Gamble HS, Mauntel R, Huang M (2001) Physics and compact modeling of SOI substrates with buried ground plane (GPSOI) for substrate noise suppression. In: Microwave symposium digest. IEEE, pp 1877–1880Google Scholar
  125. 125.
    Stefanou S, Hamel JS, Baine P, Bain M, Armstrong BM, Gamble HS, Kraft M, Kernhadjian HA, Osman K (2002) Cross-talk suppression Faraday cage structure in siliconon-insulator. In: Proc IEEE int SOI conf. IEEE, pp 181–182Google Scholar
  126. 126.
    Sze SM (2002) Semiconductor devices: physics and technology Wiley, New YorkGoogle Scholar
  127. 127.
    Tong Q-Y, Gösele U (1999) Semiconductor wafer bonding: science and technology. Wiley, New YorkGoogle Scholar
  128. 128.
    Tong Q-Y, Cha G, Gafiteanu R, Gösele U (1994) Low temperature direct wafer bonding. J Microelectromech Syst 3: 29–34CrossRefGoogle Scholar
  129. 129.
    Tong Q-Y, Schmidt E, Gösele U, Reiche M (1994) Hydrophobic silicon wafer bonding. Appl Phys Lett 64: 625–627ADSCrossRefGoogle Scholar
  130. 130.
    Udrea F, Garner D, Sheng K, Popescu H, Milne WI (2000) SOI power devices. Electronics and Communication Engineering Journal 12: 27–40CrossRefGoogle Scholar
  131. 131.
    Warnock JD (1995) Silicon bipolar device structures for digital applications: technology trends and future directions. IEEE Trans Electron Devices 42: 377–389ADSCrossRefGoogle Scholar
  132. 132.
    Watabe K, Akiyama H, Terashima T, Nobuto S, Yamawaki M, Hirao T (1996) A 0.8 pm high-voltage IC using newly designed 600 V lateral IGBT on thick buried-oxide SOI. In: Proc 8th int Sympos on power semiconductor devices and ICs. IEEE, pp 151154Google Scholar
  133. 133.
    Watabe K, Akiyama H, Terashima T, Okada M, Nobuto S, Yamawaki M, Asai T (1998) An 0.8—µm high-voltage IC using a newly designed 600—V lateral p-channel dual-action device on SOI. IEEE J Solid-State Circuits 33: 1423–1427CrossRefGoogle Scholar
  134. 134.
    Watanabe K, Hashimoto T, Yoshida M, Usami M, Sakai Y, Ikeda T (1992) A bonded-SOI bipolar process technology. In: Gösele U, Abe T, Haisma J, Schmidt M (eds) Semiconductor wafer bonding: science, technology and applications. Electrochem Soc, Pennington, PV 92–7, pp 443–451Google Scholar
  135. 135.
    Wiegand M, Reiche M, Gösele U (2000) Time-dependent surface properties and wafer bonding of O2plasma-treated silicon (100) surfaces. J Electrochem Soc 147: 27342740Google Scholar
  136. 136.
    Wiegand M, Reiche M, Krauter G (2002) Why does a plasma treatment prior to the wafer direct bonding increase the bonding energy of silicon wafer pairs in the low-temperature range? In: Baumgart H, Hunt CE, Bengtsson S, Abe T (eds) Semiconductor wafer bonding: science, technology and applications VI. Electrochem Soc, Pennington, PV 2001–27, pp 62–73Google Scholar
  137. 137.
    Wiget R, Burte EP, Gyulai J, Ryssel H (1993) Silicon-to-silicon direct bonding — characterization of the interface and manufacture of p-i-n diodes. Proc 5th European conf on power electronics and applications. Eur Power Electron Assoc, pp 63–68Google Scholar
  138. 138.
    Wilson R, Gamble HS, Mitchell SJN (1992) Improvement of silicon power device characteristics using bonding technology. In: Gösele U, Abe T, Haisma J, Schmidt M Application of Bonded Wafers to the Fabrication of Electronic Devices 261 (eds) Semiconductor wafer bonding: science, technology and applications. Electrochem Soc, Pennington, PV 92–7, pp 433–442Google Scholar
  139. 139.
    Wilson R, Quinn C, McDonnell B, Blackstone S, Yallup K (1995) Bonded and trenched SOI with buried silicide layers. In: Hunt CE, Baumgart H, Iyer SS, Abe T, Gösele U (eds) Semiconductor wafer bonding: physics and applications III. Electrochem Soc, Pennington, PV 95–7, pp 535–545Google Scholar
  140. 140.
    Wolf S (2002) Silicon-on-insulator (SOI) technology. In: Advanced silicon processing — 2002. Lattice Press, Sunset Beach, pp 1–68Google Scholar
  141. 141.
    Wondrak W, Stein E, Held R (1992) Influence of the backgate-voltage on the breakdown-voltage of SOI power devices. In: Gösele U, Abe T, Haisma J, Schmidt M (eds) Semiconductor wafer bonding: science, technology and applications. Electrochem Soc, Pennington, PV 92–7, pp 427–432Google Scholar
  142. 142.
    Xu S, Plikat R, Constapel R, Korec J, Silber D (1997) Bidirectional LIGBT on SOI substrate with high frequency and high temperature capability. In: Proc 9th int Sympos on power semiconductor devices and ICs. IEEE, pp 37–40Google Scholar
  143. 143.
    Yallup K (1993) Analog CMOS circuits on thick film SOI. In: Schmidt MA, Abe T, Hunt CE, Baumgart H (eds) Semiconductor wafer bonding: science, technology and applications II. Electrochem Soc, Pennington, PV 93–29, p 117Google Scholar
  144. 144.
    Yamaguchi, H, Fujino S, Hattori T, Hamakawa Y (1995) Superjunction by wafer direct bonding. Jpn J Appl Phys 34: L199ADSCrossRefGoogle Scholar
  145. 145.
    Yano K, Honarkhah S, Salama CAT (2001) Lateral SOI static induction rectifiers. In: Proc 13th int Sympos on power semiconductor devices and ICs. IEEE, pp 247–250Google Scholar
  146. 146.
    Yasuhara N, Funaki H, Matsudai T, Nakagawa A (1996) Experimental verification of large current capability of lateral IEGTs on SOI. In: Proc 8th int Sympos on power semiconductor devices and ICs. IEEE, pp 97–100Google Scholar
  147. 147.
    Yindeepol W, Bashir R, McGregor JM, Brown KC, De Wolf I, De Santas J, Ahmed A (1998) Defect free deep trench isolation for high voltage bipolar application on SOI wafer. In: Proc IEEE int SOI conf IEEE, pp 151–152Google Scholar
  148. 148.
    Yonehara T (2002) ELTRAN (SOI-Epi wafer) technology. In: Iyer SS, AubertonHery•AJ (eds) Silicon wafer bonding technology for VLSI and MEMS applications. Institution of Electrical Engineers, London, pp 53–81CrossRefGoogle Scholar
  149. 149.
    Yun C, Kim S, Kwon Y, Kim T (1998) High-performance 1200 V PT IGBT with improved short-circuit immunity. In: Proc 10th int Sympos on power semiconductor devices and ICs. IEEE, pp 261–26Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • A. W. Nevin

There are no affiliations available

Personalised recommendations