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Wafer Bonding pp 157-191 | Cite as

Wafer Bonding for High-Performance Logic Applications

  • K. W. Guarini
  • H.-S. P. Wong
Part of the Springer Series in MATERIALS SCIENCE book series (SSMATERIALS, volume 75)

Abstract

Shrinking the metal-oxide-semiconductor field-effect transistor (MOSFET) beyond the 50 nm technology node requires innovations to circumvent barriers due to the fundamental physics that constrains the conventional MOSFET. These innovations generally fall into two categories: new materials and new devices. Figure 5.1 depicts one view of the possible path of technological progress starting from present day 100 nm feature size technology [1,2]. In many instances, these new materials and new devices require new fabrication processes to enable their use.

Keywords

Device Layer SiGe Layer Wafer Bonding Strained Silicon Silicon Channel 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • K. W. Guarini
  • H.-S. P. Wong

There are no affiliations available

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