Silicon pp 375-398 | Cite as

Silicon Nanoelectronics: the Next 20 Years

  • L. Risch


According to Moore’s law, which predicts a decrease in feature sizes by a factor of 0.7 every 3 years, silicon transistors have become smaller and smaller in order to achieve higher integration densities, higher speed, lower power consumption and lower costs. This has been accomplished very successfully in the last 20 years, but will it continue in future? The latest ITRS, international technology roadmap for semiconductors (2001), describes in detail structural and electrical values for the scaling of CMOS down to the 22 nm node. Without any doubt, CMOS is considered to remain the mainstream technology for logic and memory. Many challenges have to be addressed for these CMOS generations regarding lithography, metallization, power dissipation and circuit design. Focusing on the device, the mandatory improvement in performance will be the key issue for further downscaling. Limitations arising from basic physical laws are still far away and will become important only well below sizes of ten nanometers.


Gate Voltage Gate Length SiGe Layer Subthreshold Slope Drain Region 
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  1. 1.
    International Technology Roadmap for Semiconductors 2001,SEMATEC, Austin, TX (2001)Google Scholar
  2. 2.
    J.T. Wallmark: Fundamental physical limitations in integrated electronic circuits. Solid State Devices, 1974 Conference Series 25, 133 (1975)Google Scholar
  3. 3.
    R.W. Keyes: Physical limits in digital electronics. Proceedings of the IEEE 63 (1975) No. 5, p. 740CrossRefGoogle Scholar
  4. 4.
    L. Risch, H. Fischer, F. Hofmann, H. Schäfer, M. Eller, T. Aeugle: Fabrication and electrical characterisation of Si/SiGe p-channel MOSFETs with a delta doped boron layer. Proceedings of the 26th European Solid State Device Research Conference (ESSDERC) (1996) p. 465Google Scholar
  5. 5.
    T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, T. Maeda, S. Takagi: Design for scaled thin film strained-SOI CMOS devices with higher carrier mobility. International Electron Devices Meeting, Technical Digest (2002) p. 31Google Scholar
  6. 6.
    R. Oberhuber, G. Zandler, P. Vogl: Subband structure and mobility of two-dimensional holes in strained Si/SiGe MOSFET’s. Physical Review B 58 (15), 9941 (1998)CrossRefGoogle Scholar
  7. 7.
    K. Rim, S. Koester, M. Hargrove, J. Chu, P.M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill, H.-S.P. Wong: Strained Si NMOSFETs for high performance CMOS technology. Symposium on VLSI Technology (2001) p. 59Google Scholar
  8. 8.
    J.L. Hoyt, H.M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E.A. Fitzgerald, D.A. Antoniadis: Strained silicon MOSFET technology. International Electron Devices Meeting, Technical Digest (2002) p. 23Google Scholar
  9. 9.
    T. Schulz, W. Rösner, L. Risch, U. Langmann: 50 nm vertical sidewall transistors with high doping concentrations. International Electron Devices Meeting, Technical Digest (2000) p. 61Google Scholar
  10. 10.
    L. Risch, W.H. Krautschneider, F. Hofmann, H. Schäfer: Vertical MOS transistors with 70nm channel length. Proceedings of the 25th European Solid State Device Research Conference (ESSDERC) (1995) p. 101Google Scholar
  11. 11.
    J.M. Hergenrother, D. Monroe, F.P. Klemens, A. Kornblit, G.R. Weber, W.M. Mansfield, M.R. Baker, F.H. Baumann, K.J. Bolan, J.E. Bower, N.A. Ciampa, R.A. Cirelli, J.I. Colonell, D.J. Eaglesham, J. Frackoviak, H.J. Gossmann, M.L. Green, S.J. Hillenius, C.A. King, R.N. Kleinman, W.Y.-C. Lai, J.T.-C. Lee, R.C. Liu, H.L. Maynard, M.D. Morris, S.-H. Oh, C.-S. Pai, C.S. Rafferty, J.M. Rosamilia, T.W. Sorch, H.-H. Vuong: The vertical replacement-gate (VRG) MOSFET: a 50 nm vertical MOSFET with lithography-independent gate length. International Electron Devices Meeting, Technical Digest (2000) p. 75Google Scholar
  12. 12.
    J.P. Colinge: SOI Technology: Materials to VLSI, 2nd edn ( Kluwer, Boston, MA 1997 )Google Scholar
  13. 13.
    L. Dreeskornfeld, J. Hartwich, E. Landgraf, R.J. Luyken, W. Rösner, T. Schulz, M. Städele, D. Schmitt-Landsiedel, L. Risch: Comparison of partially and fully depleted SOI transistors down to the sub-50nm gate length regime. The Electrochem. Soc. Proc.: SOI Technology and Devices XI, vol. 2003–05 (2003), p. 361Google Scholar
  14. 14.
    R.J. Luyken, M. Städele, W. Rösner, T. Schulz, J. Hartwich, L. Dreeskornfeld L. Risch: Perspectives of fully-depleted SOI transistors down to 20 nm gate length. Proceedings of 2002 IEEE International SOI Conference 10/02, p. 137Google Scholar
  15. 15.
    H.S.P. Wong: Beyond the conventional MOSFET. Proceedings of ESSDERC (2001) p. 69Google Scholar
  16. 16.
    S. Monfray, T. Skotnicki, B. Tavel, Y. Morand, S. Descombes, A. Talbot, D. Dutartre, C. Jenny, P. Mazoyer, R. Palla, F. Leverd, Y. Le Friec, R. Pantel, M. Haond, C. Charbuillet, C. Vizioz, D. Louis, N. Buffet: SON (silicon-onnothing) P-MOSFETs with totally silicided (CoSi2) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels. International Electron Devices Meeting, Technical Digest (2002) p. 263Google Scholar
  17. 17.
    X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, C. Hu: Sub 50 nm FinFET: PMOS. International Electron Devices Meeting, Technical Digest (1999) p. 67Google Scholar
  18. 18.
    E. Landgraf, W. Rösner, R.J. Luyken: High on current in quasi double gate transistors with undoped channel region. Proceedings of the 31th European Solid State Device Research Conference (ESSDERC) (2001) p. 271Google Scholar
  19. 19.
    H. Seidl, M. Gutsche, U. Schroeder, A. Birner, T. Hecht, S. Jakschik, J. Luetzen, M. Kerber, S. Kudelka, T. Popp, A. Orth, H. Reisinger, A. Saenger, K. Schupke, B. Sell: “A fully integrated Al2O3 trench capacitor DRAM for sub-100 nm technology. International Electron Devices Meeting, Technical Digest (2002) p. 839Google Scholar
  20. 20.
    J.D. Choi, S.-S. Cho, Y.-S. Yim, J.-D. Lee, H.-S. Kim, K.-J. Joo, S.-H. Hur, H.-S. Im, J. Kim, J.-W. Lee, K. Ill Seo, M.-S. Kang, K.-H. Kim, J.-L. Nam, K.-C. Park, M.-Y. Lee: Highly manufacturable 1 Gb Nand Flash using 0.12-pm process technology. International Electron Devices Meeting, Technical Digest (2001) p. 211Google Scholar
  21. 21.
    B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, D. Finzi: NROM: A novel localized trapping, 2-bit nonvolatile memory cell. IEEE Electron Device Letters 21, 543 (2000)CrossRefGoogle Scholar
  22. 22.
    G.E. Moore: Progres in Digital Integrated Electronics. International Electron Devices Meeting, Technical Digest (1975) p. 11Google Scholar
  23. 23.
    J.D. Meindl: “Ultra large scale integration. IEEE Transactions in Electron Devices ED-31, No. 11, 1555 (1984)Google Scholar
  24. 24.
    A. Hokazono, K. Ohuchi, M. Takayanagi, Y. Watanabe, S. Magoshi, Y. Kato, T. Shimizu, S. Mori, H. Oguma, T. Sasaki, H. Yoshimura, K. Miyano, N. Yasutake, H. Suto, K. Adachi, H. Fukui, T. Watanabe, N. Tamaoki, Y. Toyoshima, H. Ishiuchi: 14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide. International Electron Devices Meeting, Tecnical Digest (2002) p. 639Google Scholar
  25. 25.
    B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R.A. Roy, O. Dokumaci, Z. Ren, F.-F. Jamin, L. Shi, W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E.C. Jones, R.J. Miller, H.-S.P. Wong, W. Haensch: Extreme scaling with ultra-thin Si channel MOSFETs. International Electron Devices Meeting, Technical Digest (2002) p. 267Google Scholar
  26. 26.
    M. Staedele: Influence of source—drain tunneling on the subthreshold behavior of sub-10 nm double-gate MOSFETs. Proceedings of ESSDERC (2002) p. 135Google Scholar
  27. 27.
    Y. Takahashi, H. Namatsu, K. Kurihara, K. Iwdate, M. Nagase, K. Murase: Size dependence of the characteristics of Si single electron transistors on SIMOX substrates. IEEE Transactions on Electron Devices 43, No. 8, 1213 (1996)CrossRefGoogle Scholar
  28. 28.
    W. Rösner, F. Hofmann, T. Vogelsang, L. Risch: Simulation of single electron circuits. Microelectronic Engineering 27 (1–4), 55 (1995)CrossRefGoogle Scholar
  29. 29.
    C.P. Collier, E.W. Wong, M. Belohradskÿ, F.M. Raymo, J.F. Stoddart, P.J. Kuekes, R.S. Williams, J.R. Heath: Electronically configurable molecular-based logic gates. Science 285, 391 (1999)CrossRefGoogle Scholar
  30. 30.
    R.J. Luyken, F. Hofmann: Concepts for hybrid CMOS—molecular non-volatile memories. Nanotechnology 14 (2), 273 (2003)CrossRefGoogle Scholar
  31. 31.
    P. Avouris, J. Appenzeller, V. Derycke, R. Martel, S. Wind: Carbon nanotube electronics. International Electron Devices Meeting, Technical Digest (2002) p. 281Google Scholar

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© Springer-Verlag Berlin Heidelberg 2004

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  • L. Risch

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