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Silicon pp 375-398 | Cite as

Silicon Nanoelectronics: the Next 20 Years

  • L. Risch
Chapter

Abstract

According to Moore’s law, which predicts a decrease in feature sizes by a factor of 0.7 every 3 years, silicon transistors have become smaller and smaller in order to achieve higher integration densities, higher speed, lower power consumption and lower costs. This has been accomplished very successfully in the last 20 years, but will it continue in future? The latest ITRS, international technology roadmap for semiconductors (2001), describes in detail structural and electrical values for the scaling of CMOS down to the 22 nm node. Without any doubt, CMOS is considered to remain the mainstream technology for logic and memory. Many challenges have to be addressed for these CMOS generations regarding lithography, metallization, power dissipation and circuit design. Focusing on the device, the mandatory improvement in performance will be the key issue for further downscaling. Limitations arising from basic physical laws are still far away and will become important only well below sizes of ten nanometers.

Keywords

Gate Voltage Gate Length SiGe Layer Subthreshold Slope Drain Region 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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© Springer-Verlag Berlin Heidelberg 2004

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  • L. Risch

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