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High Signal-to-Noise Ratio DRAM Design and Technology

  • Kiyoo Itoh
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 5)

Abstract

One of the main contributions to DRAM advances is the one-transistor, one-capacitor (1-T) cell, as explained in Chaps. 1 and 3. The cell has been universally used for over 25 years, because it has the highest density. The drawbacks — no gain and the existence of leakage currents in the cell — have been overcome by successive developments in high signal-to-noise (S/N) ratio designs and technologies. Moreover, the multidivision of data lines by using multilevel metal wiring, explained in Chap. 3 has allowed not only a highspeed and low-power array, but also a high S/N array, while limiting the increase in chip area. Without high S/N designs and technologies, the kilobit and megabit eras would not have been developed at all. In the multigigabit era, however, there are many challenges to realizing high S/N cell design to cope with the ever-decreasing cell area and ultra-low-voltage operations. The development of higher-permittivity materials for capacitor dielectric films, while keeping the fabrication process as simple as possible, and the suppression of the random design-parameter variations of MOSFETs, which are prominent below 0.1 μm, are good examples. However, it will be more difficult than ever to accomplish these things, because of fabrication and physical limits.

Keywords

Signal Voltage Reference Voltage Data Line Soft Error Sense Amplifier 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Kiyoo Itoh
    • 1
  1. 1.Central Research LaboratoryHitachi Ltd.Kokubunji-shi, TokyoJapan

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