An Introduction to Memory Chip Design

  • Kiyoo Itoh
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 5)


Several essential inventions and innovations, and subsequent sustained efforts [1.1] toward high densities have paved the way to large-scale integrated circuit (LSI) memories, as shown in Fig. 1.1 [1.2]. Since two epoch-making announcements accompanying the start of LSI memory production in 1970 [the first extensive usage of a semiconductor memory chip for the IBM 370 mainframe computers, and the first sales of a 1-Kb dynamic random access memory (DRAM), named the 1103, from Intel], the increase in memory chip capacity has skyrocketed with the help of the ever-higher-density MOS/CMOS design and technology. The resultant LSI memories have given computers, networks, and almost everything with electrical components the benefit of a dramatically reduced cost per bit and far superior performance. Data processors and data terminals, such as personal computers, workstations, and POS terminals, as well as telephone exchanges, digital televisions, and numerical control machines, could not have been produced without them.


Threshold Voltage Data Line Flash Memory Charge Pump Read Operation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1.1]
    L.M. Terman, “Memory at ISSCC”, ISSCC Commemorative Supplement to the Digest of Technical Papers, pp. 91–111, Feb. 1993.Google Scholar
  2. [1.2]
    H. Sunami, “Coping with Memory-Cell Miniaturization by Using New Materials”, Nikkei Microdevices, pp. 144–157, Dec. 1997.Google Scholar
  3. [1.3]
    T. Murotani et al., “A 4-Level Storage 4 Gb DRAM”, ISSCC Dig. Tech. Papers, pp. 74–75, Feb. 1997.Google Scholar
  4. [1.4]
    R.H. Dennard, “Field-Effect Transistor Memory”, U.S. Patent 3387286, June 4, 1968.Google Scholar
  5. [1.5]
    F.M. Wanlass, CT. Sah, “Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes”, ISSCC Dig. Tech. Papers, pp. 32–33, Feb. 1963.Google Scholar
  6. [1.6]
    D.F. Benchkowsky, “A Fully-Decoded 2048-bit Electrically-Programmable MOS ROM”, ISSCC Dig. Tech. Papers, pp. 80–81, Feb. 1971.Google Scholar
  7. [1.7]
    Nikkei Electronics, No. 694, pp. 83–102, July 14, 1997.Google Scholar
  8. [1.8]
    Final Worldwide Semiconductor Market Share, 1995 and 1998, and Worldwide Memory Market Share, 1993 to 1995, Dataquest.Google Scholar
  9. [1.9]
    K. Itoh, VLSI Memory Design (Baifukan, Tokyo 1994) (in Japanese).Google Scholar
  10. [1.10]
    Calculated with data for 64 Mb DRAMs presented at ISSCC91, ISSCC92, ESSCIRC 92 and ESSCIRC 93.Google Scholar
  11. [1.11]
    Calculated with data for a 16 Mb CMOS SRAM presented at ISSCC 92.Google Scholar
  12. [1.12]
    T. Takeshima et al., “A 3.3 V Single-Power-Supply 64 Mb Flash Memory with Dynamic Bit-Line Latch Programming Scheme”, ISSCC Dig. Tech. Papers, pp. 148–149, Feb. 1994.Google Scholar
  13. [1.13]
    H.K. Burke, G.J. Michon, “Charge Pump Random-Access Memory”, ISSCC Dig. Tech. Papers, pp. 16–17, Feb. 1972.Google Scholar
  14. [1.14]
    W. Martino, B.F. Croxon, “The Inverting Cell Concept for MOS Dynamic RAMs”, ISSCC Dig. Tech. Papers, pp. 12–13, Feb. 1972.Google Scholar
  15. [1.15]
    W.M. Regitz, J. Karp, “A Three-Transistor-Cell, 1024- Bit, 500 NS MOS-RAM”, ISSCC Dig. Tech. Papers, pp. 42–43, Feb. 1970.Google Scholar
  16. [1.16]
    J.A. Karp et al., “A 4096- Bit Dynamic MOS RAM”, ISSCC Dig. Tech. Papers, pp. 10–11, Feb. 1972.Google Scholar
  17. [1.17]
    K. Itoh, IEEE J. Solid-State Circuits 25(3), 778 (1990).CrossRefGoogle Scholar
  18. [1.18]
    T. Masuhara et al., IEICE Trans. E74(1), 130 (1991).Google Scholar
  19. [1.19]
    Y. Nakagome, K. Itoh, IEICE Trans. E74(4), 779 (1991).Google Scholar
  20. [1.20]
    K. Itoh, “Reviews and Prospects of Deep Sub-Micron DRAM Technology”, SSDM91, Extended Abstracts, pp. 468–471, Aug. 1991.Google Scholar
  21. [1.21]
    K. Itoh et al., IEEE Proc. 83(4), 524 (1995).CrossRefGoogle Scholar
  22. [1.22]
    K. Itoh et al., IEEE J. Solid-State Circuits 32(5), 624 (1997).CrossRefGoogle Scholar
  23. [1.23]
    K. Itoh, “Ultralow-Voltage Memory Circuits”, VLSI’97, Tutorial, Gramado (Brazil), Aug. 1997.Google Scholar
  24. [1.24]
    K. Itoh et al., Electrochem. Soc. Proc. 98(1), 350 (1998).Google Scholar
  25. [1.25]
    H. Masuda et al., IEEE Trans. Electron. Devices ED-27(8), 1607 (1980).CrossRefGoogle Scholar
  26. [1.26]
    H. Masuda et al., IEEE J. Solid-State Circuits SC-15(5), 846 (1980).CrossRefGoogle Scholar
  27. [1.27]
    Y. Kawamoto et al., “A 1.28 μm2 bit-line shielded memory cell technology for 64 Mb DRAMs”, Symp. VLSI Technol. Dig. Tech. Papers, pp. 13–14, June 1990.Google Scholar
  28. [1.28]
    Y. Nakagome et al., IEEE J. Solid-State Circuits 26(4), 465 (1991).CrossRefGoogle Scholar
  29. [1.29]
    M. Takada, T. Enomoto, IEICE Trans. E74(4), 827 (1991).Google Scholar
  30. [1.30]
    K. Ishibashi, IEICE Trans. E79-C(6) 724 (1996).Google Scholar
  31. [1.31]
    M. Minami et al., “A 6.93-μm2 n-Gate Full CMOS SRAM Cell Technology with High-performance 1.8 V Dual-Gate CMOS for Peripheral Circuits”, Symp. VLSI Technol. Dig. Tech. Papers, pp. 13–14, June 1995.Google Scholar
  32. [1.32]
    K. Ishibashi et al., “A 300 MHz 4 Mb Wave-Pipeline CMOS SRAM Using a Multi-Phase PLL”, ISSCC Dig. Tech. Papers, pp. 308–309, Feb. 1995.Google Scholar
  33. [1.33]
    F. Masuoka et al., “A New Flash EEPRO M Cell using Triple Polysilicon Technology”, IEDM Tech. Dig., pp. 464–467, Dec. 1984.Google Scholar
  34. [1.34]
    F. Masuoka et al., IEICE Trans. E74(4), 868 (1991).Google Scholar
  35. [1.35]
    P. Pavan et al., IEEE Proc. 85(8), 1248 (1997).CrossRefGoogle Scholar
  36. [1.36]
    H. Kume, Oyo Buturi 65(11), 1114, (1996) (in Japanese).Google Scholar
  37. [1.37]
    V.N. Kynett et al., “An in-system reprogrammable 256 K CMOS Flash memory”, ISSCC Dig. Tech. Papers, pp. 132–133, Feb. 1988.Google Scholar
  38. [1.38]
    S. Haddad et al., Electron Device Letters, 11(11), 514 (1990).CrossRefGoogle Scholar
  39. [1.39]
    F. Masuoka et al., “New ultra high density EPRO M and Flash EEPRO M cell with NAND structure cell”, IEDM Dig. Tech. Papers, pp. 552–555, 1987.Google Scholar
  40. [1.40]
    H. Onoda et al., “Anovel cell structure suitable for a 3 V operation, sector erase FLASH memory”, IEDM Dig. Tech. Papers, pp. 599–602, 1992.Google Scholar
  41. [1.41]
    H. Kume et al., “A 1.28 μm2 contactless memory cell technology for a 3 V- only 64 Mbit EEPROM”, IEDM Dig. Tech. Papers, pp. 991–993, 1992.Google Scholar
  42. [1.42]
    M. Baur et al., “A Multilevel-Cell 32 Mb Flash Memory”, ISSCC Dig. Tech. Papers, pp. 132–133, Feb. 1995.Google Scholar
  43. [1.43]
    Nonvolatile Semiconductor Memory Technology, W.D. Brown, J.E. Brewer, Editors, IEEE PRESS, 1997.Google Scholar
  44. [1.44]
    K. Itoh et al., “VLSI Memory Technology: Current Status and Future Trends”, ESSCIRC’99 Dig. Tech. Papers, pp. 3–10, Sept. 1999.Google Scholar
  45. [1.45]
    Kirihata et al, “A 390 mm2 16 Bank 1 Gb DDR SDRAM with Hybrid Bitline Architecture”, ISSCC99 Dig. Tech. Papers, pp. 420–421, Feb. 1999.Google Scholar
  46. [1.46]
    S. Takase, N. Kushiyama, “A 1.6 GB/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme”, ISSCC99 Dig. Tech. Papers, pp. 410–411, Feb. 1999.Google Scholar
  47. [1.47]
    O. Takahashi et al., “1 GHz Fully Pipelined 3.7 ns Address Access Time 8k × 1024 Embedded DRAM Macro”, ISSCC Dig. Tech. Papers, pp. 396–397, Feb. 2000.Google Scholar
  48. [1.48]
    H. Nambu et al., “A 550-ps Access, 900-MHz, 1- Mb ECL-CMOS SRAM”, Symp. VLSI Circuits, June 1999.Google Scholar
  49. [1.49]
    For example, SRAM chips in ISSCC Dig. Tech. Papers, Feb. 1999 and 2000.Google Scholar
  50. [1.50]
    A. Nozoe et al., “A 256 Mb Multilevel Flash Memory with 2 MB/s Program Rate for Mass Storage Applications”, ISSCC99 Dig. Tech. Papers, pp. 110–111, Feb. 1999.Google Scholar
  51. [1.51]
    K. Imamiya et al., “A 130 mm2 256 Mb NAND Flash with Shallow Trench Isolation Technology”, ISSCC99 Dig. Tech. Papers, pp. 112–113, Feb. 1999.Google Scholar
  52. [1.52]
    Byung-Gil Jeon et al, “A 0.4 μm 3.3 V 1T1C 4 Mb Nonvolatile Ferroelectric RAM with Fixed Bit-line Reference Voltage Scheme and Data Protection Circuit”, ISSCC Dig. Tech. Papers, pp. 272–273, Feb. 2000.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Kiyoo Itoh
    • 1
  1. 1.Central Research LaboratoryHitachi Ltd.Kokubunji-shi, TokyoJapan

Personalised recommendations