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A Sequential DLX Design

  • Silvia Melitta Mueller
  • Wolfgang J. Paul
Chapter

Abstract

IN THE remainder of this book we develop a pipelined DLX machine with precise interrupts, caches and an IEEE-compliant floating point unit. Starting point of our designs is a sequential DLX machine without interrupt processing, caches and floating point unit. The cost effectiveness of later designs will be compared with the cost effectiveness of this basic machine.

Keywords

Cycle Time Memory Access Data Path Register File Load Operation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Silvia Melitta Mueller
    • 1
  • Wolfgang J. Paul
    • 2
  1. 1.IBM Lab Böblingen - Dept. 3173BöblingenGermany
  2. 2.Fachbereich InformatikUniversität des SaarlandesSaarbrückenGermany

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