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Clean Level Monitoring in Production Lines

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Ultraclean Surface Processing of Silicon Wafers
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Abstract

To maintain the high level of cleanliness of a semiconductor fabrication line, monitoring and control techniques are indispensable. Table 19.1 shows the clean level monitoring items (particle, contamination, charge build-up and thermal and mechanical stressing), the impacts on device characteristics, and the corresponding evaluation techniques [1].

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References

  1. K. Yoneda: Wafer Clean Technology for Submicron Processing, Technical Proceedings of SEMICON/Kansai-Kyoto 91 Technology Seminar, 162 (1991).

    Google Scholar 

  2. K. Yamabe: Reliability of Ultra Thin Oxide in ULSI’s, Technical Proceedings of SEMICON/Kansai-Kyoto 90 Technology Seminar, 129 (1990).

    Google Scholar 

  3. N. Fujino, K. Hiramoto, M. Sano, K. Murakami, H. Horie, Y. Oka, and S. Sumita: Quantative Diagnostic Technique Deduced from Behavior of Heavy Metal Contamination on Silicon Wafers, Extended Abstracts of Electrochemical SnciPty Spring Meeting, 536 (1990).

    Google Scholar 

  4. K. Yamabe et al Thermally Grown Dioxide with High Reliability, Extended Abstracts of Electrochemical Society Spring Meeting, 349 (1990).

    Google Scholar 

  5. D. L. Crook: Method of Determining Reliability Screens for Time Dependent Dielectric Breakdown, Proc. Intl. Reliability Physics Symp., 8 (1979).

    Google Scholar 

  6. D. R. Wolters and J. J. van der Schoot: Dielectric Breakdown in MOS Devices Part 1: Defect Related and Intrinsic Breakdown, Philips J. Res. 40, 115 (1985).

    CAS  Google Scholar 

  7. E. Harari: Dielectric Breakdown in Electrically Stressed Thin Films of Thermal Si02, J. Appl. Phys. 40, 278 (1969).

    Article  Google Scholar 

  8. P. Capelleti, P. Ghezzi, F. Pio, and C. Riva: Proc. IEEE 1991 Intl. Conference on Microelectronic Test Structures 14 (1), 81 (1991).

    Article  Google Scholar 

  9. D. R. Wolters and J. J. van der Schoot: Dielectric Breakdown in MOS Devices Part II: Conditions for the Intrinsic Breakdown, Philips J. Res. 40, 137 (1985).

    CAS  Google Scholar 

  10. K. Yoneda, K. Okuma, K. Hagiwara, and Y. Todokoro: The Reliability Evaluation of Thin Silicon Dioxide Using the Stepped Current TDDB Technique, J. Electrochem. Soc. 142 (2), 596 (1995).

    Article  CAS  Google Scholar 

  11. K. Okada, S. Kawasaki, and Y. Hirofuji: New Experimental Findings on Stress Induced Leakage Current on Ultrathin Silicon Dioxides, Ext. Abstr. of the 1994 Int. Conf. on SSDM, 565–567 (1994).

    Google Scholar 

  12. K. Okada, H. Kubo, A. Ishinaga, and K. Yoneda: A New Prediction Method for Oxide Lifetime and Its Application to Study Dielectric Mechanism, Digests of Technical Papers of Symposium on VLSI Technology (to be published June 1998 ).

    Google Scholar 

  13. W. H. Nicollian and J. R. Brews: MOS Physics and Technology, 435, Wiley Inter-Science (1982).

    Google Scholar 

  14. T. Namura, K. Ishikawa, N. Aoki, Y. Fukuzaki, Y. Todokoro, and M. Inoue: Evaluation of Device Charging in Ion Implantation, Jpn. J. Appl. Phys. B30 (11), 3223 (1991).

    Article  Google Scholar 

  15. K. Mameno, A. Nishida, H. Nagasawa, H. Fujisawa, K. Suzuki, and K. Yoneda: Elimination of Negative Charge-up During High Current Ion Implantation, IEICE Trans. Electron., 77 (3), 459 (1994).

    Google Scholar 

  16. H. Kubo, T. Namura, K. Yoneda, H. Oishi, and Y. Todokoro: Quantitative Charge Build-up Evaluation Technique by Using MOS Capacitors with Charge Collecting Electrodes in Wafer Processing, IEICE Trans. Electron. 79 (2), 198 (1996).

    Google Scholar 

  17. T. Sasaki, M. Kohno, S. Hirase, I. Nakatani, and T. Kusuda: Non-contact, Electrode-Free Capacitance/Voltage Measurement Based on General Theory of Metal-Oxide-Semiconductor (MOS) Structure, Jpn. J. Appl. Phys. 32, Part I, No. 9A, 4005 (1993).

    Google Scholar 

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© 1998 Springer-Verlag Berlin Heidelberg

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Yoneda, K. (1998). Clean Level Monitoring in Production Lines. In: Hattori, T. (eds) Ultraclean Surface Processing of Silicon Wafers. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-03535-1_19

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  • DOI: https://doi.org/10.1007/978-3-662-03535-1_19

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-08272-6

  • Online ISBN: 978-3-662-03535-1

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