This is the first chapter of this book to use the theoretical investigation of cornrnunication complexity in Chapter 2 in order to give lower bounds for sorne realistic parallel cornputations. This chapter is devoted to the relation between communication complexity and the complexity rneasures of Boolean circuits. More precisely, we show which lower bounds can be derived on the complexity rneasures of Boolean circuits cornputing a Boolean function f if one knows a lower bound on the cornrnunication complexity of f. The complexity measures considered are the layout area of Boolean circuits, the combinational complexity (number of gates (processors)) of Boolean circuits, and the depth (computing time) of Boolean circuits. To derive lower bounds on layout area and combinational complexity we use a standard application of communication complexity based on cutting a circuit into two parts and claiming that the circuit has to be large because of the necessary amount of information which must flow between these two circuit parts. To get a lower bound on the depth of Boolean circuits computing a specific function we need to introduce communication complexity of relations, which slightly differs from the communication complexity model investigated in Chapter 2.


Boolean Function Planar Graph Communication Complexity Combinational Complexity Concentric Representation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Juraj Hromkovič
    • 1
  1. 1.Institut für Informatik und Praktische MathematikUniversität KielKielGermany

Personalised recommendations