Abstract
The demand of multiplication intensive applications like those in the domain of digital signal processing was the driving force for embedding multipliers as hard blocks into the fabric of FPGAs. Modern FPGAs also include pre and post adders around the multiplier which is then commonly called a DSP block.
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© 2016 Springer Fachmedien Wiesbaden
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Kumm, M. (2016). Optimization of Hybrid Adder Graphs Containing Embedded Multipliers. In: Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays. Springer Vieweg, Wiesbaden. https://doi.org/10.1007/978-3-658-13323-8_8
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DOI: https://doi.org/10.1007/978-3-658-13323-8_8
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Publisher Name: Springer Vieweg, Wiesbaden
Print ISBN: 978-3-658-13322-1
Online ISBN: 978-3-658-13323-8
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