Skip to main content

Logikentwurf

  • Chapter
  • 79 Accesses

Part of the book series: Springer-Lehrbuch ((SLB))

Zusammenfassung

Die Aufgabe des Logikentwurfs besteht darin, Verhaltensbeschreibungen kombinatorischer Schaltungen (Schaltnetze) in Strukturbeschreibungen auf Gatterebene umzusetzen, die bezüglich einer vorgegebenen Zielfunktion optimiert sind. Die resultierenden Netzlisten bilden dann die Grundlage der Realisierung in einer bestimmten Zieltechnologie (vgl. die Bilder 2.36, 2.44 und 2.57).

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   54.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   69.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Literatur

  1. R. Ashenhurst: The Decomposition of Switching Functions; Proc. Int. Symp. on the Theory of Switching Functions, S. 74–116, 1959.

    Google Scholar 

  2. P. Abouzeid, K. Sakouti, G. Saucier, F. Poirot: Multilevel Synthesis Minimizing the Routing Factor; Proc. 27th Design Automation Conf., S. 365–368, 1990.

    Google Scholar 

  3. W. Au, D. Weise, S. Seligman: Automatic Generation of Compiled Simulations through Program Specialization; Proc. 28th Design Automation Conf., S. 205–210, 1991.

    Google Scholar 

  4. B. Babba, M. Crastes, G. Saucier: Input Driven Synthesis on PLDs and PGAs; Proc. 3rd European Design Automation Conf., S. 48–52, 1990.

    Google Scholar 

  5. B. Baum, H. Lipp: Ein verallgemeinertes Totzeitmodell unter Berücksichtigung von übergangsabhängigen und trägen Verzögerungen; ntz-Archiv, Band 11, S. 53–62,1989.

    Google Scholar 

  6. R. Bryant, D. Beatty, K. Brace, K. Cho, T. Sheffler: COSMOS: A Compiled Simulator for MOS Circuits; Proc. 24th Design Automation Conf., S. 9–16, 1987.

    Google Scholar 

  7. K. Bartlett, D. Bostick, G. Hachtel, R. Jacoby, M. Lightner, P. Moceyunas, C. Morrison, D. Ravenscroft: BOLD: A Multiple-Level Logic Optimization System; Digest of Papers, Int. Conf. on Computer-Aided Design, 1987.

    Google Scholar 

  8. K. Bartlett et al.: Multi-level Logic Minimization Using Implicit Don’t Cares; IEEE Trans. on Computer-Aided Design, Band CAD-7, S. 723–740, 1988.

    Article  Google Scholar 

  9. R. Brayton, J. Cohen, G. Hachtel, B. Trager, D. Yun: Fast Recursive Boolean Function Manipulation; Proc. Int. Symp. on Circuits and Systems, S. 49–54, 1982.

    Google Scholar 

  10. Z. Barzilai, J. Carter, B. Rosen, J. Rutledge: HSS — A High-Speed Simulator; IEEE Trans. on Computer-Aided Design, Band CAD-6, S. 601–616, 1987.

    Article  Google Scholar 

  11. J. Beister: A Unified Approach to Combinational Hazards; IEEE Trans. on Computers, Band C-23, S. 566–575,1974.

    Article  MATH  MathSciNet  Google Scholar 

  12. M. Berkelaar, J. Jess: Gate Sizing in MOS Digital Circuits with Linear Programming; Proc. 1st European Design Automation Conf., S. 217–221, 1990.

    Google Scholar 

  13. R. Bergamaschi: SKOL: A System for Logic Synthesis and Technology Mapping; IEEE Trans. on Computer-Aided Design, Band CAD-10, S. 1342–1355, 1991.

    Article  Google Scholar 

  14. J. Benkoski, A. Strojwas: The Role of Timing Verification in Layout Synthesis; Proc. 28th Design Automation Conf., S. 612–619, 1991.

    Google Scholar 

  15. S. Brown, R. Francis, J. Rose, Z. Vranesic: Field-Programmable Gate Arrays; Kluwer, Boston, 1992.

    Book  MATH  Google Scholar 

  16. D. Bostick, G. Hachtel, R. Jacoby, M. Lightner, P. Moceyunas, C. Morrison, D. Ravenscroft: The Boulder Optimal Logic Design System; Digest of Papers, Int. Conf. on Computer-Aided Design, S. 62–65, 1987.

    Google Scholar 

  17. R. Brayton, G. Hachtel, C. McMullen, A. Sangiovanni-Vincentelli: Logic Minimization Algorithms for VLSI Synthesis; Kluwer, Boston, 1984.

    Book  MATH  Google Scholar 

  18. D. Bochmann, F. Dresig, B. Steinbach: A New Decomposition Method for Multilevel Circuit Design; Proc. 2nd European Design Automation Conf., 1991.

    Google Scholar 

  19. E. Bolender, H. Lipp: Timing Verification: A New Understanding of False Paths; Proc. 3rd European Conf. Design Automation, S. 383–387, 1992.

    Google Scholar 

  20. M. Breuer, A. Friedman: Diagnosis and Reliable Design of Digital Systems; Computer Science Press, Woodland Hills, 1976.

    Google Scholar 

  21. R. Brayton, G. Hachtel, A. Sangiovanni-Vincentelli: Multilevel Logic Synthesis; Proc. of the IEEE, Band 78, S. 264–300, 1990.

    Article  Google Scholar 

  22. D. Brand, V. Iyengar: Timing Analysis Using Functional Analysis; IEEE Trans. on Computers, Band C-37, S. 1309–1314, 1988.

    Article  MATH  MathSciNet  Google Scholar 

  23. R. Brayton, C. McMullen: The Decomposition and Factorization of Boolean Expressions; Proc. 1982 Int. Symp. on Circuits and Systems, S. 49–54, 1982.

    Google Scholar 

  24. R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, A. Wang: MIS: A Multiple-Level Logic Optimization System; IEEE Trans. on Computer-Aided Design, Band CAD-6, S. 1062–1081,1987.

    Article  Google Scholar 

  25. R. Bryant: Graph-Based Algorithms for Boolean Function Manipulation; IEEE Trans. on Computers, Band C-35, S. 677–691, 1986.

    Article  MATH  Google Scholar 

  26. P. Camurati, P. Prinetto: Formal Verification of Hardware Correctness: An Introduction; in Computer Hardware Description Languages and their Applications, M. R. Barbacci, C. J. Koomen (Hrsg.), S. 225–247, 1987.

    Google Scholar 

  27. K.-C. Chen, S. Muroga: Input Assignment Algorithm for Decoded-PLA’s with Multi-Input Decoders; Digest of Papers, Int. Conf. on Computer-Aided Design, S. 474–477,1988.

    Google Scholar 

  28. K.-C. Cheng, S. Muroga: Timing Optimization for Multi-Level Combinational Networks; Proc. 27th Design Automation Conf., S. 339–344, 1990.

    Google Scholar 

  29. M. Chandrasekhar, J. Privitera, K. Conradt: Application of Term Rewriting Techniques to Hardware Design Verification; Proc. 24th Design Automation Conf., S. 277–282, 1987.

    Google Scholar 

  30. J. Cohoon, S. Sahni: Heuristics for the Circuit Realization Problem; Proc. 20th Design Automation Conf., S. 560–566, 1983.

    Google Scholar 

  31. M. Dagenais, V. Agarwal, N. Rumin: McBOOLE: A New Procedure for Exact Logic Minimization; IEEE Trans. on Computer-Aided Design, Band CAD-5, S. 229–238, 1986.

    Article  Google Scholar 

  32. A. Dunlop, V. Agrawal, D. Deutsch, M. Jukl, P. Kozak, M. Wiesel: Chip Layout Optimization Using Critical Path Weighting; Proc. 21st Design Automation Conf., S. 133–136,1984.

    Google Scholar 

  33. J. Darringer, D. Brand, J. Gerbi, W. Joyner, L. Trevillyan: LSS: A System for Production Logic Synthesis; IBM J. on Research and Development, Band 28, S. 537–545,1984.

    Google Scholar 

  34. S. Devadas, A. Newton: Exact Algorithms for Output Encoding, State Assignment, and Four-Level Boolean Minimization; IEEE Trans. on Computer-Aided Design, Band CAD-10, S. 13–27, 1991.

    Article  Google Scholar 

  35. E. Detjens, G. Gannot, R. Rudell, A. Sangiovanni-Vincentelli, A. Wang: Technology Mapping in MIS; Digest of Papers, Int. Conf. on Computer-Aided Design, S. 116–119, 1987.

    Google Scholar 

  36. F. Dresig, P. Lanchès, O. Rettig, U. Baitinger: Functional Decomposition for Universal Logic Cells Using Substitution; Proc. 3rd European Conf. on Design Automation, S. 38–42, 1992.

    Google Scholar 

  37. D. Du, S. Yen, S. Ghanta: On the General False Path Problem in Timing Analysis; Proc. 26th Design Automation Conf., S. 555–560, 1989.

    Google Scholar 

  38. S. Ercolani, G. DeMicheli: Technology Mapping for Electrically Programmable Gate Arrays; Proc. 28th Design Automation Conf., S. 234–239, 1991.

    Google Scholar 

  39. R. Francis, J. Rose, K. Chung: Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays; Proc. 27th Design Automation Conf., S. 613–619, 1990.

    Google Scholar 

  40. R. Francis, J. Rose, Z. Vranesic: Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs; Proc. 28th Design Automation Conf., S. 227–233, 1991.

    Google Scholar 

  41. J. Galiay, Y. Crouzet, M. Verginault: Physical versus Logical Fault Models in MOS LSI Circuits; IEEE Trans. on Computers, Band C-29, S. 527–531, 1980.

    Article  Google Scholar 

  42. M. Garey, D. Johnson: Computers and Intractability; Freeman, New York 1979.

    MATH  Google Scholar 

  43. D. Gregory, K. Bartlett, A. de Geus, G. Hachtel: SOCRATES: A System for Automatically Synthesizing and Optimizing Combinational Logic; Proc. 23rd Design Automation Conf., S. 79–85, 1986.

    Google Scholar 

  44. J. Gimpel: A Method of Producing a Boolean Function Having an Arbitrarily Prescribed Prime Implicant Table; IEEE Trans. on Electronic Computers, Band EC-14, S. 485–488, 1965.

    Article  MATH  Google Scholar 

  45. W. Görke: Fehlerdiagnose digitaler Schaltungen; Teubner, Stuttgart, 1973.

    MATH  Google Scholar 

  46. W. Grass: Steuerwerke — Entwurf von Schaltwerken mit Festwertspeichern; Springer, Berlin, 1978.

    Google Scholar 

  47. W. Grass, H. Lipp: LOGE — A Highly Effective System for Logic Design Automation; SIGDA Newsletter, Band 9, S. 6–13, 1979.

    Article  Google Scholar 

  48. G. Hachtel, R. Jacoby: Verification Algorithms for VLSI Synthesis; in Design Systems for VLSI Circuits, G. De Micheli, A. Sangiovanni-Vincentelli, P. Antognetti (Hrsg.), Martinus Nijhoff, 1987.

    Google Scholar 

  49. L. Hellerman: A Catalog of Three-Variable Or-Invert and And-Invert Logical Circuits; IEEE Trans. on Electronic Computers, Band EC-12, S. 198–223, 1963.

    Article  Google Scholar 

  50. M. Hermann, U. Schlichtmann: Schnelle Logiksynthese für FPGAs mit Optimierung des Zeitverhaltens; ITG-Fachberichte 122, Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, S. 125–134, 1992.

    Google Scholar 

  51. G. Hachtel, R. Jacoby, K. Keutzer, C. Morrison: On Properties of Algebraic Transformations and the Multifault Testability of Multilevel Logic; Digeśt of Papers, Int. Conf. on Computer-Aided Design, S. 422–425, 1989.

    Google Scholar 

  52. T.-T. Hwang, R. Owens, M. Irwin: Exploiting Communication Complexity for Multilevel Logic Synthesis; IEEE Trans. on Computer-Aided Design, Band CAD-9, S. 1017–1027, 1990.

    Article  Google Scholar 

  53. T. Hwang, R. Owens, M. Irwin: Efficiently Computing Communication Complexity for Multilevel Logic Synthesis; IEEE Trans. on Computer-Aided Design, Band CAD-11, S. 545–554, 1992.

    Article  Google Scholar 

  54. O. Ibarra, S. Sahni: Polynomially Complete Fault Detection Problems; IEEE Trans. on Computers, Band C-24, S. 242–249, 1975.

    Article  MATH  MathSciNet  Google Scholar 

  55. J. Ishikawa, H. Sato, M. Hiramine, K. Ishida, S. Oguri, Y. Kazuma, S. Murai: A Rule Based Logic Reorganization System LORES/EX; Proc. Int. Conf. on Computer Design, S. 262–266, 1988.

    Google Scholar 

  56. K. Karplus: Xmap: A Technology Mapper for Table-Lookup Field-Programmable Gate Arrays; Proc. 28th Design Automation Conf., S. 240–243, 1991.

    Google Scholar 

  57. K. Karplus: Amap: A Technology Mapper for Selector-Based Field-Programmable Gate Arrays; Proc. 28th Design Automation Conf., S. 244–247, 1991.

    Google Scholar 

  58. K. Keutzer, S. Malik, A. Saldanha: Is Redundancy Necessary to Reduce Delay?; Proc. 27th Design Automation Conf., S. 228–234, 1990.

    Google Scholar 

  59. U. Kebschull, E. Schubert, W. Rosenstiel: Multilevel Logic Synthesis Based on Functional Decision Diagrams; Proc. 3rd European Conf. on Design Automation; S. 43–47, 1992.

    Google Scholar 

  60. K. Keutzer: DAGON: Technology Binding and Local Optimization by DAG Mapping; Proc. 24th Design Automation Conf., S. 341–347, 1987.

    Google Scholar 

  61. D. Köhler: Computer Modeling of Logic Moduls Under Consideration of Delay and Waveshaping; Proc. of the IEEE, Band 57, S. 1294–1296, 1969.

    Article  Google Scholar 

  62. S. Lerner: Hazard Correction in Asynchronous Logic; IEEE Trans. on Electronic Computers, Band EC-14, S. 265–267, 1965.

    Article  MATH  Google Scholar 

  63. D. Lewis: Hierarchical Compiled Event-Driven Logic Simulation; Digest of Papers, Int. Conf. on Computer-Aided Design, S. 498–500, 1989.

    Google Scholar 

  64. M. Lightner, W. Wolf: Experiments in Logic Optimization; Digest of Papers, Int. Conf. on Computer-Aided Design, S. 285–289, 1988.

    Google Scholar 

  65. H.-J. Mathony, U. Baitinger: Fast Efficient Algorithms for the Factoring of Multiple Output Logic Functions; Proc. 1988 Int. Symp. on Circuits and Systems, S. 1851–1854,1988.

    Google Scholar 

  66. J.-C. Madre, J.-P. Billon: Proving Circuit Correctness Using Formal Comparison Between Expected and Extracted Behaviour; Proc. 25th Design Automation Conf., S. 205–210, 1988.

    Google Scholar 

  67. F. Mailhot, G. DeMicheli: Technology Mapping Using Boolean Matching and Don’t Care Sets; Proc. 1st European Design Automation Conf., S. 212–216, 1990.

    Google Scholar 

  68. Maly 87a W. Maly: Realistic Fault Modeling for VLSI Testing; Proc. 24th Design Automation Conf., S. 173–180, 1987.

    Google Scholar 

  69. P. Marwedel: Synthese und Simulation von VLSI-Systemen; Hanser, München, 1993.

    MATH  Google Scholar 

  70. H.-J. Mathony: Universal Logic Design Algorithm and its Application to the Synthesis of Two-Level Switching Circuits; IEE Proc., Teil E, Band 136, S. 171–177, 1989.

    Google Scholar 

  71. P. McGeer, R. Brayton, A. Sangiovanni-Vincentelli, S. Sahni: Performance Enhancement through the Generalized Bypass Transform; Digest of Papers, Int. Conf. on Computer-Aided Design, S. 184–187, 1991.

    Google Scholar 

  72. P. McGeer, R. Brayton: Consistency and Observability Invariance in Multi-Level Logic Synthesis; Digest of Papers, Int. Conf. on Computer-Aided Design, S. 426–429, 1989.

    Google Scholar 

  73. P. McGeer, R. Brayton: Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network; Proc. 26th Design Automation Conf., S. 561–567,1989.

    Google Scholar 

  74. P. McGeer, R. Brayton: Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications; Kluwer, Boston, 1991.

    Google Scholar 

  75. E. McCluskey: Minimization of Boolean Functions; Bell System Technical J., S. 1417–1427,1956.

    Google Scholar 

  76. E. McCluskey: Logic Design Principles with Emphasis on Testable Semicustom Circuits; Prentice-Hall, Englewood Cliffs, 1986.

    Google Scholar 

  77. K. Mei: Bridging and Stuck-At Faults; IEEE Trans. on Computers, Band C-23, S. 720–727,1974.

    Google Scholar 

  78. S. Mensch, H. Lipp: Fuzzy Specification of Finite State Machines; Proc. 1st European Design Automation Conf., S. 622–626, 1990.

    Google Scholar 

  79. R. Murgai, Y. Nishizaki, N. Shenoy, R. Brayton, A. Sangiovanni-Vincentelli: Logic Synthesis for Programmable Gate Arrays; Proc. 27th Design Automation Conf., S. 620–625,1990.

    Google Scholar 

  80. T. Mott: Determination of the Irredundant Normal Forms of a Truth Function by Iterated Consensus of the Prime Implicants; IRE Trans. on Electronic Computers, Band EC-9, S. 245–252,1960.

    Google Scholar 

  81. S. Malik, A. Wang, R. Brayton, A. Sangiovanni-Vincentelli: Logic Verification Using Binary Decision Diagrams in a Logic Synthesis Environment; Digest of Papers, Int. Conf. on Computer-Aided Design, S. 6–9, 1988.

    Google Scholar 

  82. R. Nelson: Simplest Normal Truth Functions; J. of Symbolic Logic, Band 20, S. 105–108,1955.

    Article  MATH  Google Scholar 

  83. Octtools Distribution 4.0; Electronics Research Laboratory, University of California, Berkeley, 1990.

    Google Scholar 

  84. P. Paulin, F. Poirot: Logic Decomposition Algorithms for the Timing Optimization of Multi-Level Logic; Proc. Int. Conf. on Computer Design, S. 329–333,1989.

    Google Scholar 

  85. M. Pedram, N. Bhat: Layout Driven Technology Mapping; Proc. 28th Design Automation Conf., S. 99–105, 1991.

    Google Scholar 

  86. J. Rajski, J. Vasudevamurthy: The Testability-Preserving Concurrent Decomposition and Factorization of Boolean Expressions; IEEE Trans. on Computer-Aided Design, Band CAD-11, S. 778–793,1992.

    Google Scholar 

  87. J. Roth, R. Karp: Minimization over Boolean Graphs; IBM J. on Research and Development, Band 6, S. 227–238,1962.

    Article  MathSciNet  Google Scholar 

  88. A. Ruehli, P. Wolff, G. Goertzel: Power and Timing Optimization of Large Digital Systems; Proc. Int. Symp. on Circuits and Systems, S. 402–405, 1976.

    Google Scholar 

  89. S. Sahni, A. Bhatt: The Complexity of Design Automation Problems; Proc. 17th Design Automation Conf., S. 402–411, 1980.

    Google Scholar 

  90. J. Saul, B. Eschermann, J. Frößl: Two-Level Logic Circuits Using EXOR Sums of Products; IEE Proc, Teil E, 1993.

    Google Scholar 

  91. T. Sasao: Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays; IEEE Trans. on Computers, Band C-30, S. 635–643,1981.

    Google Scholar 

  92. G. Saucier, P. Sicard, L. Bouchet: Multi-Level Synthesis on PALs; Proc. 1st European Design Automation Conf., S. 542–546, 1990.

    Google Scholar 

  93. A. Saldanha, R. Brayton, A. Sangiovanni-Vincentelli, K-T. Cheng: Timing Optimization with Testability Considerations; Digest of Papers, Int. Conf. on Computer-Aided Design, S. 460–463, 1990.

    Google Scholar 

  94. S. Smith, M. Mercer, B. Brock: Demand Driven Simulation: BACKSIM; Proc. 24th Design Automation Conf., S. 181–187, 1987.

    Google Scholar 

  95. B. Steinbach, Le T. C: Entwurf testbarer Schaltungen; Wiss. Schriftenreihe der Technischen Universität Chemnitz, Heft 12/1990.

    Google Scholar 

  96. K. Singh, A. Wang, R. Brayton, A. Sangiovanni-Vincentelli: Timing Optimization of Combinational Logic; Digest of Papers, Int. Conf. on Computer-Aided Design, S. 282–285, 1988.

    Google Scholar 

  97. C. Timoc et al.: Logical Models of Physical Failures; Proc. Int. Test Conf., S. 546–553,1983.

    Google Scholar 

  98. J. Vasudevamurthy, J. Rajski: A Method for Concurrent Decomposition and Factorization of Boolean Expressions; Digest of Papers, Int. Conf. on Computer-Aided Design, S. 510–513, 1990.

    Google Scholar 

  99. E. Veitch: A Chart Method for Simplifying Boolean Functions; Proc. of the ACM S. 127–133, Mai 1952.

    Google Scholar 

  100. R. Wadsack: Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits; Bell System Technical J., Band 57, S. 1449–1474, 1978.

    MATH  Google Scholar 

  101. Z. Wang, P. M. Maurer: LECSIM: A Levelized Event Driven Compiled Logic Simulator; Proc. 27th Design Automation Conf., S. 491–496, 1990.

    Google Scholar 

  102. C.-L. Wey, T.-Y. Chang: PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs; Proc. 25th Design Automation Conf., S. 421–426, 1988.

    Google Scholar 

  103. M. Weyerer, G. Goldemund: Prüfbarkeit elektronischer Schaltungen; Teubner, Stuttgart, 1988.

    Google Scholar 

  104. S. Wendt: Nachrichtentechnik Band III, Nachrichtenverarbeitung; Springer, Berlin, 1982.

    Google Scholar 

  105. R. Wei, A. Sangiovanni-Vincentelli: PROTEUS: A Logic Verification System for Combinational Circuits; Proc. Int. Test Conf., S. 350–359, 1986.

    Google Scholar 

  106. L. Wang, N. Hoover, E. Porter, J. Zasio: SSIM: A Software Levelized Compiled-Code Simulator; Proc. 24th Design Automation Conf., S. 2–8, 1987.

    Google Scholar 

  107. H. Wojtkowiak: Test und Testbarkeit digitaler Schaltungen; Teubner, Stuttgart, 1988.

    Google Scholar 

  108. N. Woo: A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility; Proc. 28th Design Automation Conf., S. 248–251, 1991.

    Google Scholar 

  109. H.-J. Wunderlich: Hochintegrierte Schaltungen: Prüfgerechter Entwurf und Test; Springer, Berlin, 1991.

    Book  Google Scholar 

  110. K. Yoshikawa, H. Ichiryu, H. Tanishita, S. Suzuki, N. Nomizu, A. Kondoh: Timing Optimization on Mapped Circuits; Proc. 28th Design Automation Conf., S. 112–117, 1991.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 1993 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Eschermann, B. (1993). Logikentwurf. In: Funktionaler Entwurf digitaler Schaltungen. Springer-Lehrbuch. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-95710-9_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-95710-9_4

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-56788-2

  • Online ISBN: 978-3-642-95710-9

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics