A VLSI Chess Legal Move Generator
Constructing a chess legal move generator (LMG) illustrates the design and evaluar tion of a variety of algorithms and the problems encountered implementing them in VLSI. Software-based algorithms for LMG and their possible hardware implementations are examined. Several new approaches exploiting parallelism and systolic structure are developed. The implementations of several algorithms are compared: the space, time, complexity, and feasibility tradeoffs provide interesting insights into the development of custom-designed VLSI circuits for non-numeric applications.
KeywordsFinite State Machine Legal Move Input Message Output Message Chess Board
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