A VLSI Chess Legal Move Generator

  • Jonathan Schaeffer
  • P. A. D. Powell
  • Jim Jonkman
Conference paper


Constructing a chess legal move generator (LMG) illustrates the design and evaluar tion of a variety of algorithms and the problems encountered implementing them in VLSI. Software-based algorithms for LMG and their possible hardware implementations are examined. Several new approaches exploiting parallelism and systolic structure are developed. The implementations of several algorithms are compared: the space, time, complexity, and feasibility tradeoffs provide interesting insights into the development of custom-designed VLSI circuits for non-numeric applications.


Sorting Tame Goldwater 


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Copyright information

© Computer Science Press, Inc. 1983

Authors and Affiliations

  • Jonathan Schaeffer
    • 1
  • P. A. D. Powell
    • 1
  • Jim Jonkman
    • 1
  1. 1.VLSI Research Group, Institute for Computer ResearchUniversity of WaterlooWaterlooCanada

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