System-Related Aspects of Testing

  • J. Armaos
  • W. Glunz
  • B. Hanstein
  • M. Johansson
  • M. Pabst
  • H. Severloh
Conference paper

Abstract

For the complex electronic systems of today, efficient test methods are required. This paper surveys design for testability and test data generation techniques applicable to different kinds of digital systems. In particular, the concept of modular testing, test strategy planning (knowledge-based selection of optimal test method combinations), and automatic synthesis of testable systems are discussed.

Keywords

Paration Sarna 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [Abad 85]
    M. S. Abadir, M. A. Breuer: A Knowledge-based System for Designing Testable VLSI Chips. IEEE Design and Test of Computers, 1985.Google Scholar
  2. [Abad 89]
    M. S. Abadir: TIGER: Testability Insertion Guidance Expert System. ICCAD, 1989.Google Scholar
  3. [Beck 85]
    B. Becker: An Easily Testable Optimal-time VLSI Multiplier. Proc. Euromicro’85.Google Scholar
  4. [Been 86]
    F. Beenker, K. Eerdewijk, R. Gerritsen, F. Peacock, M. van der Star: Macro Testing: Unifying IC and Board Test. IEEE Design & Test, Dec. 1986.Google Scholar
  5. [Been 89]
    F. Beenker, R. Dekker, R. Stans, M. van der Star: A Testability Strategy for Silicon Compilers. Int. Test Conf., 1989.Google Scholar
  6. [Bhaw 89]
    S. Bhawmik, P. Palchaudhuri: DFT EXPERT: Designing Testable VLSI Circuits. IEEE Design & Test of Computers, Oct. 1989.Google Scholar
  7. [Brgl 89]
    F. Brglez, D. Bryan, J. Calhoun, G. Kedem, R. Lisanke: Automated Synthesis for Testability. IEEE Trans. on Industrial Electronics, Vol. 36, No. 2, pp. 263–277, May 1989.CrossRefGoogle Scholar
  8. [Camp 89]
    R. Camposano, W. Rosenstiel: Synthesizing Circuits from Behavioural Descriptions. IEEE Trans. on Computer-Aided Design, Vol. 8, No. 2, 1989.Google Scholar
  9. [Cat 89]
    F. Catthor, J. van Sas, L. Inze, H. De Man: A Testability Strategy for Multiprocessor Architecture. IEEE Design & Test, April 1989.Google Scholar
  10. [Cosg 88]
    S. J. Cosgrove, N. Burgess, G. Musgrave: TEXAS: A Testing Methodology Guided by AI Techniques. IEEE Colloquium on DFT, 1988.Google Scholar
  11. [Dekk 88]
    R. Dekker, F. Beenker, L. Thijssen: Fault Modelling and Test Algorithm Development for Static Random Access Memories. Int. Test Conf. 1988.Google Scholar
  12. [Deva 88a]
    S. Devadas, H.-K. T. Ma, A. R. Newton, A. SangiovanniVincentelli: Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines. Proc. ITC 1988, pp. 621–630.Google Scholar
  13. [Deva 88b]
    S. Devadas, H.-K. T. Ma, A. R. Newton, A. Sangiovanni-Vincentelli: Optimal logic synthesis and testability: Two faces of the same coin. Proc. ITC 1988, pp. 4–12.Google Scholar
  14. [Disl 88]
    C. Dislis, I. D. Dear, D. C. Law, J. Miles, A. P. Ambler, K. A. E. Totton: Cost Effective Test Strategy Selection. IFIP Workshop on Knowledge-based Systems for Test and Diagnosis, Grenoble, 1988.Google Scholar
  15. [Eich 77]
    E. B. Eichelberger, T. W. Williams: A logic design structure for LSI testability. Proc. DAC 1977, pp. 462–468.Google Scholar
  16. [Fung 86]
    H. S. Fung, S. Hirschhorn: An Automatic DFT System for the Silc Silicon Compiler. IEEE Design and Test of Computers, 1986.Google Scholar
  17. [Gajs 83]
    D. Gajsky, H. Kuhn: Guest Editors Introduction: New VLSI Tools. Computer, Dec. 1983.Google Scholar
  18. [Gebo 88]
    C. H. Gebotys, M. I. Elmasry: VLSI Design and Synthesis with Testability. Design Automation Conf. 1988.Google Scholar
  19. [Gern 84]
    M. Gerner, H. Nertinger: Scan Path in CMOS Semicustom LSI chips?. Proc. ITC 1984.Google Scholar
  20. [Gupt 89]
    R. Gupta, R. Gupta, M. Breuer: An Efficent Implementation of the BALLAST Partial Scan Architecture. Proc. IFIP Conf. VLSI89, pp 133–142.Google Scholar
  21. [Hall 89]
    J. J. Hallenbeck, J. R. Cybrynski, N. Kanopoulos, T. Markas, N. Vasanthavada: The Test Engineer’s Assistant. Computer, April 1989.Google Scholar
  22. [Hapk 89]
    F. Hapke: Automatic Test Program Generation for a Block Oriented VLSI Chip Design. European Test Conf., 1989.Google Scholar
  23. [Hoer 86]
    E. Hörbst, M. Nett, H. Schwärtzel: VENUS- Entwurf von VLSI-Schaltungen. Springer-Verlag, Berlin 1986.Google Scholar
  24. [Hoer 89]
    E. Hürbst et al.: Synthese-Die Entwurfsmethode der Zukunft. Elektronik 1989, Heft 23.Google Scholar
  25. [Jone 86]
    N. A. Jones, K. Baker: An Intelligent Knowledge-based System Tool for High-level BIST Design. Int. Test Conf., 1986.Google Scholar
  26. [JTAG 88]
    Joint Test Action Group Proposal, version 2.0, 1988.Google Scholar
  27. [Kim 88]
    K. Kim, J. G. Tront, D. S. Ha: Automatic Insertion of BIST Hardware Using VHDL. Design Automation Conf. 1988.Google Scholar
  28. [Kras 88]
    A. Krasniewski, S. Pilarski: Circular self-test path: A low-cost BIST technique. Proc. DAC 1988, pp. 407–415.Google Scholar
  29. [Leve 89]
    R. Leveugle, G. Saucier: Synthesis of Dedicated Controllers for Concurrent Checking. Proc. IFIP Conf. VLSI89, pp 123–132.Google Scholar
  30. [Ligt 89]
    M. Ligthart, R. Stans: A Fault Model for PLAs. European test Conf. 1989.Google Scholar
  31. [Mang 85]
    T. E. Mangir: EXCAT: An Expert System for Testable Design of VLSI. Int. Symp. on VLSI Technology, Systems and Applications, 1985.Google Scholar
  32. [Marh 89a]
    M. Marhoefer: Allocation of test hardware within high level synthesis. 12th Annual IEEE Workshop on Design for Testability, Vail (CO), April 18–21, 1989.Google Scholar
  33. [Marh 89b]
    M. Marhoefer: Methods and Tools for Automatic Design for Testability- A-Survey-. Siemens internal report.Google Scholar
  34. [Masu 85]
    T. Masui, F. Niimi, M. Iwase: A new approach to design for testability in an LSI logic synthesis system. Proc. ICCAD-85, pp. 105–107.Google Scholar
  35. [McCI 85a]
    E. J. McCluskey: Built-in self-test techniques. IEEE Design and Test, April 1985, pp. 21–28.Google Scholar
  36. [McC185b]
    E. J. McCluskey: Built-in self-test structures. IEEE Design and Test, April 1985, pp. 29–36.Google Scholar
  37. [Roth 89]
    W. Roth, M. Johansson, W. Glunz: The BED Concept-A Method and a Language for Modular Test Generation. VLSI’ 89.Google Scholar
  38. [Sama 86]
    M. A. Samad, J. A. B. Fortes: DEFT-A Design for Testability Expert System. Fall Joint Computer Conf. 1986.Google Scholar
  39. [Schm 86]
    D. Schmid, R. Camposano, A. Kunzmann, W. Rosenstiel, H.-J. Wunderlich: The Integration of Test and High Level Synthesis in a General Design Environment. Proc. ICTC 86, pp 317–331.Google Scholar
  40. [Schu 87]
    M. H. Schulz, E. Trischler, T. M. Safert: SOCRATES-A Highly Efficient Automatic Test Pattern Generation System. Proceedings of the International Test Conference 1987.Google Scholar
  41. [Schu 89]
    M. H. Schulz, E. Auth: ESSENTIAL-An Efficient Self-Learning Test Pattern Generation Algorithm for Sequential Circuits. Proceedings of the International Test Conference 1989.Google Scholar
  42. [Stro 88]
    C. E. Stroud: Automated BIST for sequential logic synthesis. IEEE Design & Test of Computers, December 1988, p. 22–32.Google Scholar
  43. [Tris 80]
    E. Trischler: Incomplete Scan Path with an Automatic Test Generation Methodology. Proc. ITC 1980, pp. 153–162.Google Scholar
  44. [Wund 85]
    H.-J. Wunderlich: PROTEST: A Tool for Probabilistic Testability Analysis. Proc. DAC 1985.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1990

Authors and Affiliations

  • J. Armaos
    • 1
  • W. Glunz
    • 1
  • B. Hanstein
    • 1
  • M. Johansson
    • 1
  • M. Pabst
    • 1
  • H. Severloh
    • 1
  1. 1.Applied Computer Science and Software Systems Design AutomationSiemens Corporate Research and DevelopmentMunichGermany

Personalised recommendations