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A Compiler Technique for Modelling Multiprocessor Systems Utilising Microprocessors of Arbitrary Architecture

  • B. H. Rudall
  • R. F. W. Coates
  • N. T. Shepheard

Abstract

A powerful, flexible and machine portable compiler is described which provides both a simulation base and assembly capabilities for microprocessors of arbitrary architecture. The compiler utilises the STAGE 2 macroprocessor and the ISP defining notation and is of particular importance in that it permits a realistic simulation of multiprocessor systems created from microprocessor arrays.

Keywords

Basis Operation Host Computer Multiprocessor System Assembly Capability Discontinuous Process 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© The World Organisation of General Systems and Cybernetics 1978

Authors and Affiliations

  • B. H. Rudall
    • 2
  • R. F. W. Coates
    • 2
  • N. T. Shepheard
    • 1
    • 2
  1. 1.School of Mathematics and Computer Science BangorBangor, N. WalesUK
  2. 2.School of Electronic Engineering ScienceBangor, N. WalesUK

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