GaAs Digital Integrated Circuits for Ultra High Speed LSI/VLSI

  • R. C. Eden
  • B. M. Welch
Part of the Springer Series in Electrophysics book series (SSEP, volume 5)

Abstract

The principal requirements of a digital integrated circuit technology to make possible the development of ultra-high speed, very large scale integration (VLSI) circuits are: (1) very high density (low chip area per gate), (2) low gate power dissipation, (3) extremely low dynamic switching energy (speed-power product), (4) high speed (very low gate propagation delay) and (5) very high process yield (sufficient to achieve useable chip yields of such complex parts). These factors are not listed here according to priority; no priority is possible since all of these requirements must be met if such very high performance VLSI circuits are to be realized. The origins of most of these requirements are obvious. Clearly, large numbers of gates (104 to 105) cannot be placed on a reasonable sized (~1 cm2) chip unless the gate areas are small (<~1000 μm2/gate). The power per gate must be low (<<1 mW) if chip dissipations are to remain manageable. As illustrated in Table I, the requirement on dynamic switching energy for high speed VLSI is especially severe because this low power must be maintained at high clocking frequencies. Since the dynamic switching energy or speed-power product, 2PDτd, is the minimum energy that a gate can dissipate during a cycle (two transitions), the power dissipation for a chip with Ng gates with an average gate clocking frequency of fc will be
$$ {P_{{chip}}} \geqslant 2{N_{g}}{f_{c}}({P_{D}}{\tau _{d}}) $$
(1)
.

Keywords

Microwave Boron Propa Milling Selenium 

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Copyright information

© Springer-Verlag Berlin Heidelberg 1982

Authors and Affiliations

  • R. C. Eden
  • B. M. Welch

There are no affiliations available

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