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GaAs Digital Integrated Circuits for Ultra High Speed LSI/VLSI

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Very Large Scale Integration (VLSI)

Part of the book series: Springer Series in Electrophysics ((SSEP,volume 5))

Abstract

The principal requirements of a digital integrated circuit technology to make possible the development of ultra-high speed, very large scale integration (VLSI) circuits are: (1) very high density (low chip area per gate), (2) low gate power dissipation, (3) extremely low dynamic switching energy (speed-power product), (4) high speed (very low gate propagation delay) and (5) very high process yield (sufficient to achieve useable chip yields of such complex parts). These factors are not listed here according to priority; no priority is possible since all of these requirements must be met if such very high performance VLSI circuits are to be realized. The origins of most of these requirements are obvious. Clearly, large numbers of gates (104 to 105) cannot be placed on a reasonable sized (~1 cm2) chip unless the gate areas are small (<~1000 μm2/gate). The power per gate must be low (<<1 mW) if chip dissipations are to remain manageable. As illustrated in Table I, the requirement on dynamic switching energy for high speed VLSI is especially severe because this low power must be maintained at high clocking frequencies. Since the dynamic switching energy or speed-power product, 2PDτd, is the minimum energy that a gate can dissipate during a cycle (two transitions), the power dissipation for a chip with Ng gates with an average gate clocking frequency of fc will be

$$ {P_{{chip}}} \geqslant 2{N_{g}}{f_{c}}({P_{D}}{\tau _{d}}) $$
((1))

.

An erratum to this chapter is available at http://dx.doi.org/10.1007/978-3-642-88640-9_11

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References

  1. R. C. Eden, B. M. Welch, and R. Zucca, “Planar GaAs IC Technology: Applications for Digital LSI,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 419–426, August 1978.

    Article  Google Scholar 

  2. P. Wolf, “Microwave Properties of Schottky-barrier Field-effect Transistors,” IBM J. Res. Develop., vol 14, pp. 125–141, Mar 1970, and other papers in that issue.

    Article  Google Scholar 

  3. S. A. Roosild, private communication of silicon MESFET characteristic curve data from Air Force Contract F19628–70-C-0094 USAF, RADC, Hanscom Field, MA. (K. E. Drangeid, IBM, principal investigator).

    Google Scholar 

  4. J. H. Yuan and E. Harari, “Short-Channel CMOS/SOS Technology,” IEEE Trans. Electron Devices, vol. ED-25, p. 989, Aug. 1978.

    Article  Google Scholar 

  5. F. F. Fang and A. B. Fowler, “Hot Electron Effects and Saturation Velocities in Silicon Inversion Layers,” J. of Appl. Phys., vol. 41, pp. 1825–1831, Mar. 15, 1970.

    Article  Google Scholar 

  6. J. G. Ruch and G. S. Kino, “Measurements of the Velocity-Field Characteristics of Gallium Arsenide,” Appl. Phys. Lett., vol. 10, p. 40, 1967.

    Article  Google Scholar 

  7. R.C. Eden, J. L. Moll, and W. E. Spicer, “Experimental Evidence for Optical Population of the X Minima in GaAs,” Phys. Rev. Lett., vol. 18, pp. 597–599, Apr. 1967.

    Article  Google Scholar 

  8. R. S. Huang and P. H. Ladbrooks, “The Physics of Excess Electron Velocity in Submicron-channel FETs,” J. Appl. Phys., vol. 48, pp. 4791–4798, Nov. 1977.

    Article  Google Scholar 

  9. T. J. Maloney and J. Frey, “Transient and Steady State Electron Transport Properties of GaAs and InP,” J. Appl. Phys., vol. 48, pp. 781–787, Feb. 1977.

    Article  Google Scholar 

  10. M. S. Shur, “Analytical Model of GaAs MESFET’s,” IEEE Trans. Electron Devices, vol. ED-25, p. 612, June 1978.

    Article  Google Scholar 

  11. J. A. Higgins, R. L. Kuvas, F. H. Eisen, and D. R. Chen, “Low-Noise GaAs FET’s Prepared by Ion Implantation,” IEEE Trans. Electron Dev., vol. ED-25, pp. 587–596, June 1978, and other papers in that issue

    Article  Google Scholar 

  12. T. Mimura, K. Odani, N. Yokoyama, Y. Nakayama, and M. Fukuta, “GaAs Microwave MOSFET’s,” IEEE Trans. Electron. Dev., vol. ED-25, pp. 573–579, June 1978.

    Article  Google Scholar 

  13. N. Yokoyama, T. Mimura, H. Kusakawa, K. Suyama and M. Fukata, “Low-Power High-Speed Integrated Logic with GaAs MOSFETs,” Digest of Tech. Papers, 1979 Int. Conf. on Solid State Devices, Tokyo, Aug. 27, 1979, pp. 31–32; to be published in Japanese J. Appl. Phys., vol 19, Feb. 1980.

    Google Scholar 

  14. R. Zucca, “Electrical Compensation in Semi-Insulating GaAs,” J. Appl. Phys., vol 48, pp. 1987–1994, May 1977.

    Article  Google Scholar 

  15. R. Zuleeg, J. K. Notthoff, and K. Lehovec, “Femtojoule High-Speed Planar GaAs E-JFET Logic,” IEEE Trans. Electron Devices, vol. ED-25, pp. 628–639, June 1978.

    Article  Google Scholar 

  16. A. A. Immorlica, Jr., and F. H. Eisen, “Planar Passivated GaAs Hyperabrupt Varactor Diodes,” Proc. Sixth Biennial Cornell Electrical Eng. Conf., August 1977, pp 151–159.

    Google Scholar 

  17. H. Morkoc, S. Bandy, R. Sankaran, G. Antypas, and R. Bell, “A Study of High-Speed Normally Off and Normally On Al0.5Ga0.5As Heterojunction Gate GaAs FET’s (HJFET),” IEEE Trans. Electron Devices, vol. ED-25, pp. 619–627, June 1978.

    Article  Google Scholar 

  18. H. Ishikawa, H. Kusakawa, K. Suyama, and M. Fukuta, “Normally-Off Type GaAs MESFET for Low-Power High-Speed Logic Circuits,” 1977 Int. Solid State Circuits Conf., Digest of Tech. Papers, Feb. 1977, pp. 200–201.

    Google Scholar 

  19. G. Bert, G. Nuzillat, and C. Arnodo, “Femtojoule Logic Circuit Using Normally-Off GaAs MESFETs,” Electron. Lett., vol. 13, pp. 644–645, Oct. 1977.

    Article  Google Scholar 

  20. M. Fukuta, K. Suyama, and H. Kusakawa, “Low Power GaAs Digital Integrated Circuits with Normally Off MESFETs,” IEEE Trans. Electron Devices, vol ED-25. p. 1340, Nov. 1978.

    Article  Google Scholar 

  21. C. A. Liechti, “GaAs FET Logic,” 1976 Intern. GaAs Symp., Inst. Phys. Conf., Ser. No. 33a, 1977, ch. 5, pp 227–236.

    Google Scholar 

  22. R. L. VanTuyl, C. A. Liechti, R. E. Lee, and E. Gowen, “GaAs MESFET Logic with 4-GHz Clock Rate,” IEEE J. Solid-State Circuits, vol. SC-12, pp. 485–496, Oct. 1977.

    Article  Google Scholar 

  23. P. T. Greiling, C. F. Krumm, F. S. Ozdemir, L. H. Hackett, and R. F. Lohr, Jr., “Electron Beam Fabricated GaAs FETs Inverter,” IEEE Trans. Electron Devices, vol. ED-25, p. 1340, Nov. 1978.

    Article  Google Scholar 

  24. R. C. Eden, B. M. Welch, and R. Zucca, “Low Power GaAs Digital ICs Using Schottky Diode-FET Logic,” 1978 Int. Solid State Circuits Conf., Digest of Tech. Papers, pp. 68–69, Feb. 1977.

    Google Scholar 

  25. B. M. Welch and R. C. Eden, “Planar GaAs Integrated Circuits Fabricated by Ion Implantation,” 1977 Int. Electron Device Meeting, Tech. Digest, Dec. 1977, pp. 205–208.

    Google Scholar 

  26. S Yanagisawa, O. Wada, and H. Takanashi, “Gigabit Rate Gunn-Effect Shift Register,” 1975 Int. Electron Devices Meeting, Tech. Digest, Dec. 1975, pp 317–319.

    Google Scholar 

  27. M. Cathelin and G. Durand, “Logic ICs Using GaAs FETs in a Planar Technology,” L’onde Electrique, vol. 58, pp. 218–221, Mar. 1978.

    Google Scholar 

  28. R. L. Van Tuyl, C. A. Liechti and C. A. Stolte, “Gallium Arsenide Digital Integrated Circuits,” Tech. Rep. AFAL-TR-76–264, Apr. 1977.

    Google Scholar 

  29. M. R. Splinter, “A 2-μm Silicon Gate CMOS/SOS Technology,” IEEE Trans. on Elect. Dev., vol. ED-25, pp. 996–1003 (1978).

    Article  Google Scholar 

  30. M. T. Elliott, M. R. Splinter, A. B. Jones, J. P. Reekstin, “Size Effects in E-Beam Fabricated MOS Devices,” 1977 Inter. Electron Device Meeting, Tech. Digest pp. 11A-B.

    Google Scholar 

  31. G. Nuzillat, C. Arnado and J. P. Puron, “A Subnanosecond Integrated Switching Circuit with MESFETs for LSI,” IEEE J. Sol id-State Circuits, vol. SC-11, pp. 385–394 (1976).

    Article  Google Scholar 

  32. T. Nakamura et. al., “Punch-Through MOSFET for High-Speed Logic,” 1978 Int. Solid-State Circuits Conf., Tech. Digest, pp. 22–23.

    Google Scholar 

  33. H. M. Darley, T. W. Houston and G. W. Taylor, “Fabrication and Performance of Submicron Silicon MESFET,” 1978 Int. Electron Devices Meeting, Tech. Digest, Dec. 1978, pp. 62–65.

    Google Scholar 

  34. R. C. Eden, “GaAs Integrated Circuits, MSI Status and VLSI Prospects,” 1978 Int. Electron Devices Meeting, Tech. Digest, Dec. 1978, pp. 6–11.

    Google Scholar 

  35. G. Bert, T. Pham Ngu, G. Nuzillat and M. Gloanec, “Quasi-Normally-Off MESFET Logic for High Performance GaAs ICs,” Paper 7 in Research Abstracts of the First Annual Gallium Arsenide Integrated Circuit Symposium, Lake Tahoe, Sept. 17, 1979.

    Google Scholar 

  36. J. K. Notthoff and C. H. Vogelsang, “Gate Design for DCFL with GaAs E-JFETs,” Paper 10 in Research Abstracts of First Annual Gallium Arsenide Integrated Circuit Symposium, Lake Tahoe, Sept. 27, 1979.

    Google Scholar 

  37. R. C. Eden, F. S. Lee, S. I. Long, B. M. Welch, and R. Zucca, “Multi-Level Logic Gate Implementation in GaAs ICs using Schottky Diode-FET Logic,”- 1980 Int. Solid State Circuits Conf., Digest of Tech. Papers, Feb. 1980.

    Google Scholar 

  38. S. I. Long, B. M. Welch, R. C. Eden, F. S. Lee and R. Zucca, “MSI High Speed Low Power GaAs Integrated Circuits,” 1979 Int. Conf. on Solid State Devices, Digest of Tech. Papers, Tokyo, Aug. 1979, pp. 29–30; to be published in Japanese J. Appl. Phys., vol. 19, No. 2, Feb. 1980.

    Google Scholar 

  39. R. C. Eden, B. M. Welch, R. Zucca and S. I. Long, “The Prospects for Ultrahigh-Speed VLSI GaAs Digital Logic,” IEEE J. Solid-State Circuits, vol. ED-26, pp. 299–317, Apr. 1979.

    Google Scholar 

  40. T. Mizutani, N. Kato, S. Ishida, K. Asai, Y. Sakakibara, K. Komatsu, and M. Ohmori, “High-Speed Enhancement-Mode GaAs MESFET Integrated Circuits,” 1979 Int. Conf. on Solid State Devices, Digest of Tech. Papers, Tokyo, Aug. 1979, pp. 33–34; to be published in Japanese J. Appl. Phys., vol 19, No. 2, Feb. 1980.

    Google Scholar 

  41. R. H. Dennard, F. H. Gaensslen, E. J. Walker and P. W. Cook, “1 μm MOSFET VLSI Technology: Part II — Device Designs and Characteristics for High-Performance Logic Applications,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 247–255, Apri. 1979

    Article  Google Scholar 

  42. R. H. Dennard, F. H. Gaensslen, E. J. Walker and P. W. Cook, “1 μm MOSFET VLSI Technology: Part II — Device Designs and Characteristics for High-Performance Logic Applications,” IEEE Trans. Electron Devices, vol. ED-26, pp. 325–333, April 1979.

    Article  Google Scholar 

  43. G. L. Troeger, A. F. Behle, P. E. Friebertshauser, K. L. Hu and S. H. Watanabe, “Fully Ion Implanted Planar GaAs E-JFET Process,” 1979-Int. Electron Devices Meeting, Tech. Digest, Dec. 1979, pp. 497–500.

    Google Scholar 

  44. P. I. Suciu, E. N. Fuls, and H. J. Boll, “High-Speed NMOS Circuits Made with X-Ray Lithography and Reactive Sputter Etching,” Electron Device Letters, vol. EDL-1, pp. 10–11, Jan. 1980.

    Article  Google Scholar 

  45. M. Gloanec, G. Nuzillat, C. Arnodo and M. Peltier, “A GaAs Integrated Edge-Triggered D-type Flip-Flop,” Digest of the First Specialty Conference on Gigabit Logic for Microwave Systems, Orlando, Fla., pp. 114–119, May 1979.

    Google Scholar 

  46. F. E. Eisen, B. M. Welch, K. Gamo, T. Inada, H. Mueller, M. A. Nicolet and J. W. Mayer, “Sulfur, Selenium and Tellurium Implantation in GaAs,” Inst. Phys. Conf. Ser. No. 28 (1976): Chap. 2.

    Google Scholar 

  47. B. M. Welch, F. E. Eisen and J. A. Higgins, “Gallium Arsenide Field Effect Transistors by Ion Implantation,” J. Appl. Physics 45, 3685, 1974.

    Article  Google Scholar 

  48. P. T. Greiling, F. S. Ozdemir, C. F. Krumm and B. F. Lohr, Jr., “Electron Beam Fabricated GaAs Integrated Circuits,” 1979 IEDM Tech. Digest.

    Google Scholar 

  49. B. M. Welch, Y. D. Shen, R. Zucca and R. C. Eden, “Planar High Yield GaAs IC Processing Techniques,” 1979 IEDM Tech. Digest.

    Google Scholar 

  50. B. M. Welch, Y. D. Shen, R. Zucca, R. C. Eden, and S. I. Long, “LSI Processing Technology for Planar GaAs Integrated Circuits,” to be published in IEEE Trans. Electron Devices, Special Issue, June, 1980.

    Google Scholar 

  51. R. E. Lundgren, C. F. Krumm and R. L. Pierson, “Fast Enhancement-Mode GaAs MESFET Logic,” 37th Ann. Dev. Research Conf., Boulder, Co. 25–27 June, 1979.

    Google Scholar 

  52. R. E. Lundgren, C. F. Krumm and R. F. John Jr., “Enhancement-Mode GaAs MESFET Logic,” Presented at the IEEE GaAs IC Symposium, Lake Tahoe, NV, Sept. 1979.

    Google Scholar 

  53. F. E. Eisen and B. M. Welch, “Radiotracer Profiles in Sulfur Implanted GaAs,” Proc. 5th International Conference on Ion Implantation in Semiconductors and Other Materials, Boulder, CO, August 1976.

    Google Scholar 

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Eden, R.C., Welch, B.M. (1982). GaAs Digital Integrated Circuits for Ultra High Speed LSI/VLSI. In: Barbe, D.F. (eds) Very Large Scale Integration (VLSI). Springer Series in Electrophysics, vol 5. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-88640-9_5

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  • DOI: https://doi.org/10.1007/978-3-642-88640-9_5

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