Abstract
With advances in semiconductor technology, integrated circuit (IC) designers will soon be putting millions of transistors in a single chip. Predictions of microelectronics researchers [44,45] at the beginning of the Very Large Scale Integration (VLSI) era were true and the continuing evolution of IC technology will result in Ultra Large Scale of Integration (ULSI) [66] in the very near future. At the beginning of this decade, Metal Oxide Semiconductor (MOS) chips utilised 5μ gate length transistors. In the middle of the decade submicron features were achieved. Scientists and engineers are predicting 0.1μ features before the 1990s. This continuous technological advance poses a real challenge to researchers working on Computer Aided Design (CAD) for integrated circuits.
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© 1991 Springer-Verlag Berlin, Heidelberg
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Jabri, M.A. (1991). Overview. In: An Artificial Intelligence Approach to Integrated Circuit Floorplanning. Lecture Notes in Engineering, vol 66. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-84489-8_1
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DOI: https://doi.org/10.1007/978-3-642-84489-8_1
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-53958-2
Online ISBN: 978-3-642-84489-8
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