Abstract
In this paper we present a tool for hierarchical layout verification. Design rule check and netlist extraction can be performed within one program run. This allows to verify more complex rules than with separated tools and avoids redundant work. To improve verification, the program preserves the original layout hierarchy: Each cell in the layout is checked only once and then replaced by an abstract, containing all information needed to check the cell against its environment on the next higher level. The program does not require restrictions concerning the layout style, however the implemented basic algorithm can be modified by user instructions to adapt it to a special design style and thereby increasing its efficiency.
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References
Gupta A., “ACE: A Circuit Extractor”, Proc. 20th. Design Automation Conference, 1983, 721–725
Gupta A., Hon R.W., “HEXT: A Hierarchical Circuit Extractor”, Journal of VLSI and Computer Systems, 1983, Vol. I, 1, 23–39
Hannken-Illjes J., Golze U., “A hierarchic incremental Designrule Checker” (in german), Informationstechnik, 3 (1986), 132–138
Hedenstierna N., Jeppson K., “New algorithms for increased efficiency in hierarchical design rule checking”, INTEGRATION, the VLSI journal, 5 (1987) 319–336
Henkel V., Golze U., “RISCE–A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification”, Proc. 25th Design Automation Conference, 1988, pp. 465–470
Hofman M., Lauther U., “HEX: An Instruction Driven Approach to Feature Extraction”, Proc. 20th Design Automation Conference, 1983, pp. 331–336
Perry S., Kalman S., Pilling D., “Edge-Based Layout Verification”, VLSI Systems Design, September 1985, 106–114
Scheffer L., Soetarman R., “Hierarchical Analysis of IC Artwork with User-Defined Rules”, IEEE Design & Test, Feb 1986, pp. 66–74
Scott W.S., Ousterhout J.K., “Magic’s Circuit Extractor”, Proc. 22nd Design Automation Conference, 1985, pp. 286–292
Tarolli G.M., Herman W.J., “Hierarchical Circuit Extraction with Detailed Parasitic Capacitance”, Proc. 20th Design Automation Conference, 1983, pp. 337–345
Wagner T., “Hierarchical Layout Verification”, Proc. 21st Design Automation Conference, 1984, pp. 484–489
Wong Y., “Hierarchical Circuit Verification”, Proc. 22nd Design Automation Conference, 1985, pp. 695–701
Yin, M. T., “Layout Verification of VLSI Designs”, VLSI Design, July 1985, pp. 30–38
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© 1990 Springer-Verlag Berlin Heidelberg
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Meier, W. (1990). Hierarchical Netlist Extraction and Design Rule Check. In: Reusch, B. (eds) Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme. Informatik—Fachberichte, vol 255. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-84304-4_2
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DOI: https://doi.org/10.1007/978-3-642-84304-4_2
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-53163-0
Online ISBN: 978-3-642-84304-4
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