Advertisement

Fault-Tolerance in Imaging-Oriented Systolic Arrays

  • R. Negrini
  • M. G. Sami
  • N. Scarabottolo
  • R. Stefanelli
Conference paper
Part of the Springer Study Edition book series (volume 41)

Abstract

Image Processing often involves convolutions and Fourier Transforms (DFT and FFT): these specific operations are well implemented by means of a systolic multi-pipeline structure.

Practical implementations require large pipelines, adopting highly integrated circuits that are prone to production defects and run-time faults; efficient fault-tolerance through reconfiguration is then required.

Still, the basic problem of concurrent (or semi-concurrent) testing must be solved prior to any reconfiguration step. Here, we prove how these structures allow to perform testing by a simple technique (based on the classical LSSD method) so that added circuits required due to testing functions is kept very limited.

Keywords

Fast Fourier Transform Discrete Fourier Transform Interconnection Network systoLic Array Conditioning Signal 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. [1]
    K.Hwang, F.A.Biggs, Computer architecture for parallel processing, McGraw-Hill, New York (1984)Google Scholar
  2. [2]
    P.Kogge, The architecture of pipeline computers, McGraw-Hill, New York (1981)Google Scholar
  3. [3]
    R.Negrini, R.Stefanelli, “Fault-tolerance techniques in array for image processing”, in Pyramidal Systems for Processing and Computer Vision, ed. V.Cantoni, S.Levialdi, pp. 373–392, Springer-Verlag (May 1986)Google Scholar
  4. [4]
    A.Antola, C.Bonzio, R.Negrini, N.Scarabottolo, G.Storti-Gajani, “SAR Real-Time on-Board Processing: the Architecture”, 2nd Int.I Conf. on Supercomputing, pp. 254–264, Santa Clara (CA)Google Scholar
  5. [5]
    O.Bruschi, R.Negrini, S.Ravaglia, “Systolic arrays for serial signal processing”, Microprocessing and Microprogramming, vol. 20, n. 1–3, pp. 133–140 (April 1987)CrossRefGoogle Scholar
  6. [6]
    T.E.Mangir, A.Avizienis, “Fault-toleranr design for VLSI: effect of interconnect requirements on yield improvement of VLSI design”, IEEETC, vol. C31, n. 7, pp. 609–615 (July 1982)Google Scholar
  7. [7]
    T.W.Williams, K.P.Parker, “Design for testability -a survey”, Proc. IEEE, vol. 71, n. 1, pp. 98–112 (Jan. 1983)CrossRefGoogle Scholar
  8. [8]
    A.Antola, “Multiple-transform pipelines for image coding”, Internal Report, Dept. Electronics, Politecnico di Milano, Milano (Sept. 1987)Google Scholar
  9. [9]
    J.H.McClellan, R.J.Purdy, “Applications of digital signal processing to radar”, in Applications of Digital Signal Processing, ed. A.V.Oppenheim, Prentice-Hall (1978)Google Scholar
  10. [10]
    R.Negrini, M.G.Sami, R.Stefanelli, “Restructuring and reconfiguring DSP mutli-pipeline arrays”, Proc. MTNS87, Phoenix (June 1987)Google Scholar
  11. [11]
    M.G.Sami, R.Stefanelli, “Fault-stealing: an approach to fault-tolerance of VLSI processing arrays”, Proc. ICCAS 1985, Beijing (June 1985)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • R. Negrini
    • 1
  • M. G. Sami
    • 1
  • N. Scarabottolo
    • 1
  • R. Stefanelli
    • 1
  1. 1.Dipartimento di ElettronicaPolitecnico di MilanoMilanoItaly

Personalised recommendations