Skip to main content
SpringerLink
Log in
SpringerLink
Log in

Basic Building Blocks of Linear SC Networks

  • Chapter
MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems

Part of the book series: Communications and Control Engineering Series ((CCE))

Abstract

Switched capacitor techniques take advantage of the excellent properties of MOS capacitors and switches and permit the realization of numerous analog sampled-data MOS circuits. Most SC circuit implementations make use of basic building blocks or cells, which are realized in many different ways. In this chapter we systematically present a diverse set of basic building blocks by separating them into a few major classes. For each circuit we determine realizable transfer functions, as well as the best way to implement them. We concentrate mainly on stray-insensitive and/or parasitic-compensated circuits because of their importance in integrated MOS realizations. We recall that a stray-(parasitic-) insensitive network is defined as a network whose desired transfer functions are not dependent upon the stray capacitances of its elements.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References and Sources for Further Reading

  1. Allen, P.E.; SAnchez-Sinencio, E.: Switched Capacitor Circuits. NewYork: Van Nostrand (1984)

    Google Scholar 

  2. Gregorian, R.; Ternes, G.C.: Analog Integrated Circuits for Signal Processing. NewYork: John Wiley (1986)

    Google Scholar 

  3. Martin, K.: New clock feedthrough cancellation technique for analogue MOS switched-capacitor circuits. Electronics Letters 18 (1982) 39–40

    Article  Google Scholar 

  4. Young, IA.; Hodges, DA.: MOS switched-capacitor analog sampled-data direct-form recursive filters. IEEE J. Solid-State Circuits SC 14 (1979) 1020–1033

    Article  Google Scholar 

  5. Maloberti, F.: Switched-capacitor building blocks for analogue signal processing. Electronics Letters 19 (1983) 263–265

    Article  Google Scholar 

  6. Gregorian, R.: High resolution switched-capacitor D/A converter. Microelectronics J. 12 (1981) 10–13

    Article  Google Scholar 

  7. Mulawka, J.J.: Switched capacitor analogue delays comprising unity gain buffer. Electronics Letters 17 (1981) 276–277

    Article  MathSciNet  Google Scholar 

  8. Gillingham, P.: Stray-free switched-capacitor unit-delay circuit. Electronics Letters 20 (1984) 308–310

    Article  Google Scholar 

  9. Enomoto, T.; Ishihara, T.; Yasumoto, M.-A.: Integrated tapped MOS analogue delay line using switched capacitor technique. Electronics Letters 18 (1982) 193–194

    Article  Google Scholar 

  10. Bingham, JA.C.: Applications of a direct-transfer SC integrator. IEEE Trans. Circuits and Systems CAS 31 (1984) 419–420

    Article  Google Scholar 

  11. Matsui, K.; Matsuura, T.; Fukasawa, S.; Izawa, Y.; Toba, Y.; Miyake, N.; Nagasawa, K.: CMOS video filters using switched capacitor 14-MHz circuits. IEEE J. Solid-State Circuits SC 20 (1985) 1096–1101

    Article  Google Scholar 

  12. Fellman, R.D.; Brodersen, R.W.: A switched-capacitor adaptive lattice filter IEEE Trans. Acoustics Speech and Signal Processing ASSP 31 (1983) 294–304

    Article  Google Scholar 

  13. Hosticka, B.J.; Dalsaß, K.-G.; Krey, D.; Zimmer, G.: Behavior of analog MOS integrated circuits at high temperatures. IEEE J Solid-State Circuits SC 20 (1985) 871–874

    Article  Google Scholar 

  14. Lee, C.C.: A new switched-capacitor realization for cyclic analog-to-digital converter. IEEE Proc. Int. Symposium on Circuits and Systems, Newport Beach, California, USA (1983) 1261–1265

    Google Scholar 

  15. Yen, R.C.; Gray, P.R.: A MOS switched-capacitor instrumentation amplifier. IEEE J. Solid-State Circuits SC 17 (1982) 1008–1013

    Article  Google Scholar 

  16. Degrauwe, M.; Vittoz, E.; Verbauwhede, I.: A micropower CMOS-instrumentation amplifier. IEEE J. Solid-State Circuits SC 20 (1985) 805–807

    Article  Google Scholar 

  17. Van Peteghem, P.M.; Verbauwhede, I.; Sansen, W.M.C.: Micropower high-performance SC building block for integrated low-level signal processing. IEEE J. Solid-State Circuits SC 20 (1985) 837–844

    Article  Google Scholar 

  18. Sansen, W.; Van Peteghem, P.; Steyaert, M.: Switched capacitor filters for biomedical signal processing. IEEE Proc. Int. Symposium on Circuits and Systems, Kyoto, Japan (1985) 243–246

    Google Scholar 

  19. Vittoz, EA.: Dynamic analog techniques, in Design of MOS VLSI Circuits for Telecommunication. Prentice Hall (1985) 145–170

    Google Scholar 

  20. Vittoz, EA.: The design of high-performance analog circuits on digital CMOS chips. IEEE J. Solid-State Circuits SC 20 (1985) 657–665

    Article  Google Scholar 

  21. Fleischer, P.E.; Ganesan, A.; Laker, K.R.: Parasitic compensated switched capacitor circuits. Electronics Letters 17 (1981) 929–931

    Article  Google Scholar 

  22. Martin, K.: Improved circuits for the realization of switched-capacitor filters. IEEE Trans. Circuits-and Systems CAS 27 (1980) 237–244

    Article  Google Scholar 

  23. Weinrichter, H.; Nossek, JA.: Switched-capacitor-filters: a comparison of the basic design principles. Proc. European Conf. on Circuit Theory and Design ECCTD 80, Warsaw, Poland (1980) 17–28

    Google Scholar 

  24. Dessoulavy, R.; Knob, A.; Krummenacher, F.; Vittoz, EA.: A synchronous switched capacitor filter. IEEE J. Solid-State Circuits SC 15 (1980) 301–305

    Article  Google Scholar 

  25. Knob, A.: Novel strays-insensitive switched-capacitor integrator realising the bilinear z-transform. Electronics Letters 16 (1980) 173–174

    Article  Google Scholar 

  26. Eriksson, S.; Akhlaghi, H.: Noninverting parasitic-compensated bilinear SC integrator with only one amplifier. Electronics Letters 19 (1983) 450–452

    Article  Google Scholar 

  27. Eriksson, S.: SC filter circuit with decimation of sampling frequency. Electronics Letters 21 (1985) 484–485

    Google Scholar 

  28. Robert, J.; Ternes, G.C.; Krummenacher, F.; Valencic, V.; Deval, P.: Offset and clockfeedthrough compensated switched-capacitor integrators. Electronics Letters 21 (1985) 941–942

    Article  Google Scholar 

  29. Sansen, W.; Van Peteghem, P.M.: An area-efficient approach to the design of very-large time constants in switched-capacitor integrators. IEEE J. Solid-State Circuits SC 19 (1984) 772–780

    Article  Google Scholar 

  30. Lam, KKK; Copeland, MA.: Noise-cancelling switched-capacitor (SC) filtering technique. Electronics Letters 19 (1983) 810–811

    Article  Google Scholar 

  31. Fischer, G.; Moschytz, G.S.: SC integrator for high-frequency applications. Electronics Letters 19 (1983) 495–496

    Article  Google Scholar 

  32. Nagaraj, K.; Singhal, K.; Viswanathan, T.R.; Vlach, J.: Reduction of finite-gain effect in switched-capacitor filters. Electronics Letters 21 (1985) 644–645

    Article  Google Scholar 

  33. Nagaraj, K.; Vlach, J.; Viswanathan, T.R.; Singhal, K.: Switched-capacitor integrator with reduced sensitivity to amplifier gain. Electronics Letters 22 (1986) 1103–1105

    Article  Google Scholar 

  34. Ternes, G.C.; Haug, K.: Improved offset-compensation schemes for switched-capacitor circuits. Electronics Letters 20 (1984) 508–509

    Article  Google Scholar 

  35. Haug, K.; Maloberti, F.; Ternes, G.C.: Switched capacitor integrators with low finite-gain sensitivity. Electronics Letters 21 (1985) 1156–1157

    Article  Google Scholar 

  36. Larson, L.E.; Ternes, G.C.: Switched-capacitor gain stage with reduced sensitivity to finite amplifier gain and offset voltage. Electronics Letters 22 (1986) 1281–1283

    Article  Google Scholar 

  37. Haug, K.; Maloberti, F.; Ternes, G.C.: Switched-capacitor circuits with low op-amp gain sensitivity. IEEE Proc. Int. Symposium on Circuits and Systems, San Jose, USA (1986) 797–800

    Google Scholar 

  38. Nagaraj, K.; Singhal, K.; Viswanathan, T.R.; Vlach, J.: Switched-capacitor circuits with reduced sensitivity to finite amplifier gain IEEE Proc. Int. Symposium on Circuits and Systems, San Jose, USA (1986) 618–621

    Google Scholar 

  39. Maloberti, F.; Montecchi, F.: An offset-compensated continuous-feedback SC integrator for biquad sections. IEEE Proc. Int. Symposium on Circuits and Systems, Montreal, Canada (1984) 1058–1061

    Google Scholar 

  40. Martin, K.; Sedra, A.S.: Effects of the op amp finite gain and bandwidth on the performance of switched-capacitor filters. IEEE Trans. Circuits and Systems CAS 28 (1981) 822–829

    Article  Google Scholar 

  41. Geiger, R.L.; Sanchez-Sinencio, E.: Operational amplifier gain-bandwidth product effects on the performance of switched-capacitor networks. IEEE Trans. Circuits and Systems CAS 29 (1982) 96–106

    Article  Google Scholar 

  42. Fischer, G.; Moschytz, G.S.: SC filters for high frequencies with compensation for fmite-gain amplifiers. IEEE Trans. Circuits and Systems CAS 32 (1985) 1050–1056

    Article  Google Scholar 

  43. Ternes, G.C.: Finite amplifier gain bandwidth effects in switched-capacitor filters. IEEE J. Solid-State Circuits SC 15 (1980) 358–361

    Article  Google Scholar 

  44. Fischer, G.; Moschytz, G.S.: On the frequency limitations of SC filters. IEEE J. Solid-State Circuits SC 19 (1984) 510–518

    Article  Google Scholar 

  45. Ribner, D.B.; Copeland, MA.: Biquad alternatives for high-frequency switched-capacitor filters. IEEE J. Solid-State Circuits SC 20 (1985) 1085–1095

    Article  Google Scholar 

  46. Hsieh, K.C.; Gray, P.R.; Senderowicz, D.; Messerschmitt, D.G.: A low-noise chopper-stabilized differential switched-capacitor filtering technique. IEEE J. Solid-State Circuits SC 16 (1981) 708–715

    Article  Google Scholar 

  47. Senderowicz, D.; Dreyer, S.F.; Huggins, J.H.; Rahim, C.F.; Laber, CA.: A family of differential NMOS analog circuits for a PCM codes filter chip. IEEE J. Solid-State Circuits SC 17 (1982) 1014–1023

    Article  Google Scholar 

  48. Maloberti, F.; Montecchi, F.; Torelli, G.; Halâsz, E.: Bilinear design of fully differential switched-capacitor ladder filters. IEE Proc. G. Electronic Circuits and Systems 132 (1985) 266–272

    Article  Google Scholar 

  49. Nairn, D.G.; Sedra, A.S.: Circuit and design techniques for fully-differential switched-capacitor filters. IEEE Proc. Int. Symposium Circuits and Systems, San Jose, California, USA (1986) 603–606

    Google Scholar 

  50. Plaza, A. de la: High-frequency switched-capacitor filter using unity-gain buffers. IEEE J Solid-State Circuits SC 21 (1986) 470–477

    Article  Google Scholar 

  51. Ananda Mohan, P.V.; Ramachandran, V.; Swamy, M.N.S.: General stray-insensitive first-order active SC network. Electronics Letters 18 (1982) 1–2

    Article  Google Scholar 

  52. Datar, R.B.; Sedra, A.S.: Exact design of strays-insensitive switched-capacitor ladder filters. IEEE Trans. Circuits and Systems CAS 30 (1983) 888–898

    Article  Google Scholar 

  53. Hökenek, E.; Moschytz, G.S.: Design of parasitic-insensitive bilinear-transformed admittance-scaled (BITAS) SC ladder filters. IEEE Trans. Circuits and Systems CAS 30 (1983) 873–888

    Article  Google Scholar 

  54. Choi, T.C.; Kaneshiro, R.T.; Brodersen, R.W.; Gray, P.R.; Jett, W.B.; Wilcox, M.: High-frequency CMOS switched-capacitor filters for communications application. IEEE J. Solid-State Circuits SC 18 (1983) 652–663

    Article  Google Scholar 

  55. Cichocki, A.; Unbehauen, R.: Simple technique for analysis of SC networks using general-purpose circuit simulation programs. Electronics Letters 22 (1986) 956–958

    Article  Google Scholar 

  56. Cichocki, A.; Strauß, F.; Unbehauen, R.: Realization of arbitrary linear resistive multiports using a switched-capacitor technique. Int. J. Electronics 60 (1986) 463–480

    Article  Google Scholar 

  57. Unbehauen, R.; Cichocki, A.: Ein Beitrag zur Synthese von SC-Netzwerken zur linearen and nichtlinearen Signalverarbeitung. NTZ Archiv 8 (1986) 271–285

    Google Scholar 

  58. Hosticka, B.J.; Moschytz, G.S.: Practical design of switched-capacitor networks for integrated circuit implementation. IEE Proc. G. Electronic Circuits and Systems 3 (1979) 76–88

    Article  Google Scholar 

  59. Horio, Y.; Mori, S.: Switched-capacitor lossless discrete differentiator with modified sampleand-hold sequence. Electronics Letters 21 (1985) 1036–1037

    Article  Google Scholar 

  60. Horio, Y.; Mori, S.: SC modified lossless discrete differentiators and resulting SC highpass ladder filters. Electronics Letters 22 (1986) 97–99

    Article  Google Scholar 

  61. Montecchi, F.: Bilinear design of high-pass switched-capacitor ladder filters. IEEE Proc. Int. Symposium on Circuits and Systems, Kyoto, Japan (1985) 547–550

    Google Scholar 

  62. Hughes, J.B.; Bird, N.C.; Soin, R.S.: A receiver IC for a 1+1 digital subscriber loop. IEEE J. Solid-State Circuits SC 20 (1985) 671–678

    Article  Google Scholar 

  63. McGuffin, B.; Liu, B.: Low sensitivity switched capacitor filters using allpass building blocks. IEEE Proc. Int. Symposium on Circuits and Systems, Montreal, Canada (1984) 288–291

    Google Scholar 

  64. Kato, K.; Takebe, T.: Variable switched-capacitor bandpass, band-elimination filters and all-pass networks. IEEE Proc. Int. Symposium on Circuits and Systems, Montreal, Canada (1984) 809–812

    Google Scholar 

  65. Gregorian, R.; Nicholson, W.E.: Switched-capacitor decimation and interpolation circuits. IEEE Trans. Circuits and Systems CAS 27 (1980) 509–514

    Article  Google Scholar 

  66. Ghaderi, M.B.; Ternes, G.C.; Law, S.: Linear interpolation using CCDs or switched-capacitor filters. Proceedings of IEE 128, Pt. G. (1981) 213–215

    Google Scholar 

  67. Martin, K.; Sedra, A.S.: Easing prefiltering requirements of S.C. filters. Electronics Letters 16 (1980) 613–614

    Article  Google Scholar 

  68. Viswanathan, T.R.; Viswanathan, T.L.: Increasing the clock frequency of switched-capacitor filters. Electronics Letters 16 (1980) 316–317

    Article  Google Scholar 

  69. Grünigen, D. von; Brugger, U.W.; Moschytz, G.S.: Simple switched-capacitor decimation circuit. Electronics Letters 17 (1981) 30–31

    Google Scholar 

  70. Grünigen, D.C. von; Sigg, R.; Ludwig, M.; Brugger, U.W.; Moschytz, G.S.; Melchior, H.: Integrated switched-capacitor low-pass filter with combined anti-aliasing decimation filter for low frequencies. IEEE J. Solid-State Circuits SC 17 (1982) 1024–1029

    Google Scholar 

  71. Da Franca, J.E.: Nonrecursive polyphase switched-capacitor decimators and interpolators. IEEE Trans. Circuits and Systems CAS 32 (1985) 877–887

    Article  MathSciNet  Google Scholar 

  72. Da Franca, J.E.; Haigh, D.G.: Design and applications of single-path frequency-translated switched-capacitor systems. IEEE Trans. Circuits and Systems CAS 35 (1988) 394–408

    Article  Google Scholar 

  73. Betts, A.K.; Taylor, J.T.; Haigh, D.G.: Synthesis method for switched-capacitor FIR decimators and interpolators. IEEE Proc. Int. Symposium on Circuits and Systems, Helsinki, Finland (1988) 2463–2466

    Google Scholar 

  74. Larson, L.E.; Ternes, G.C.: Switched-capacitor building blocks with reduced sensitivity to finite amplifier gain, bandwidth and offset voltage. IEEE Proc. Int. Symposium on Circuits and Systems, Philadelphia, USA (1987) 334–338

    Google Scholar 

  75. Ternes, G.C.: High-accuracy pipeline A/D converter configuration. Electronics Letters 21 (1985) 762–763

    Article  Google Scholar 

  76. Martin, K.; Ozcolak, L.; Lee, Y.S.; Ternes, G.C.: A differential switched-capacitor amplifier. IEEE J. Solid-State Circuits SC 22 (1987) 104–106

    Article  Google Scholar 

  77. Nagaraj, K.; Viswanathan, T.R.; Singhal, K.; Vlach, J.: Switched-capacitor circuits with reduced sensitivity to amplifier gain. IEEE Trans. Circuits and Systems CAS 34 (1987) 571–574

    Google Scholar 

  78. Matsumoto, H.; Watanabe, K.: Spike-free switched-capacitor circuits. Electronics Letters 23 (1987) 428–429

    Article  Google Scholar 

  79. Kunsagi, L.; Larson, L.E.; Ternes, G.C.; Martin, K.W.: Switched-capacitor circuits with reduced sensitivity to finite amplifier gain, bandwidth and offset voltage. Proc. European Conf. on Circuit Theory and Design ECCTD 87, Paris (1987) 543–548

    Google Scholar 

  80. Qiuting, H.: A novel technique for the reduction of capacitance spread in high-Q SC circuits. IEEE Proc. Int. Symposium on Circuits and Systems, ISCAS-88, Helsinki, Finland (1988) 1249–1252

    Google Scholar 

  81. Huang, Q.; Sansen, W.: Design techniques for improved capacitor area efficiency in switched-capacitor biquads. IEEE Trans. Circuits and Systems CAS 34 (1987) 1590–1599

    Article  Google Scholar 

  82. Bienstman, LA.; DeMan, H.J.: An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling. IEEE J. Solid-State Circuits SC 15 (1980) 1051–1059

    Article  Google Scholar 

  83. Tsividis, Y.: Signal proccessors with transfer function coefficients determined by timing. IEEE Trans. Circuits and Systems CAS 29 (1982) 807–817

    Article  Google Scholar 

  84. Lee, Y.S.; Martin, K.W.: A switched-capacitor realization of multiple FIR filters on a single chip. IEEE J. Solid-State Circuits SC 23 (1988) 536–542

    Article  Google Scholar 

  85. Nalecz, M.; Mulawka, J.J.: Parasitic-compensated building blocks for active switched-capacitor filters. IEEE Proc. Int. Symposium on Circuits and Systems, Helsinki, Finland (1988) 1483–1486

    Google Scholar 

  86. Kunsagi, L.; Ternes, G.C.: Buffer-based switched capacitor gain stages. Electronics Letters 24 (1988) 254–255

    Article  Google Scholar 

  87. Watanabe, K.; Ogawa, S.: Clock-feedthrough compensated sample/hold circuits. Electronics Letters 24 (1988) 1226–1228

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Lehrstuhl für Allgemeine und Theoretische Elektrotechnik, Universität Erlangen-Nürnberg, Cauerstraße 7, D-8520, Erlangen, Deutschland

    Prof. Dr.-Ing. Rolf Unbehauen

  2. Technical University, Koszykowa 75, PL-00-661, Warsaw, Poland

    Dr.-Ing. Andrzej Cichocki

Authors
  1. Prof. Dr.-Ing. Rolf Unbehauen
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Dr.-Ing. Andrzej Cichocki
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 1989 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Unbehauen, R., Cichocki, A. (1989). Basic Building Blocks of Linear SC Networks. In: MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems. Communications and Control Engineering Series. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-83677-0_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-83677-0_4

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-83679-4

  • Online ISBN: 978-3-642-83677-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation