Node Placement Algorithms to Display Communications Topology to Network Controllers

Abstract

When placing integrated circuits on a circuit board or macro-cells on a gate-array, there are well-defined mathematically goal functions concerned with minimizing aggregate path lengths, restricting peak path lengths, avoiding crossings, avoiding mutual couplings, avoiding current loops, etc.

Matching a display to the human operator involves very similar objectives, when concerned only with a clear representation of the abstract network topology.

In most practical systems, however, we also require to retain a reasonable relation to real geographical locations, distances and directions.

When designing a graphical man-machine interface, a compromise between geographical and topological objectives has therefore to be found, which is subjectively acceptable to the user and readily implemented in the machine.

This paper outlines two algorithms of this type, developed at SHAPE Technical Centre, i.e. node density dependent Cartesian mapping and simulated annealing, and it discusses their relative advantages and disadvantages.