Abstract
In this paper the construction of fast algorithms on sequential machines, the art of programming dedicated parallel machines and a design philosophy for dedicated image processing hardware is treated and their trade-off is discussed. Examples of different image processing systems used and built in our group are given and evaluated. The conclusions are that for each specific class of image processing operations, effort has to be put in the choice of the optimum data representation and in the means for fast access of the data structure incorporated with that representation. This holds for software as well as for hardware. For special hardware designs, effort has to be put in the interface with the host processor and in a joint programming environment of the special purpose machine and its host system.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
van Antwerpen G., van Munster R.J.; TIPS Users manual. Internal report of the Institute of Applied Physics-TNO, Delft, The Netherlands, 1987.
Arcelli A., Cordelia L., Levialdi S.; Parallel thinning of binary pictures. Electronic Letters 11, 148–149, 1975.
Boekamp R., Groen F.C.A., Gerritsen F.A., van Munster R.J.; Design and implementation of a Cellular-Logic VME processor Module. Proc. SPIE B-596, Cannes 1985.
Bohm W., (dataflow processor group, University of Manchester). Private Communication.
Buurman J., Duin R.P.W., Jonker P.P.; A comparison of scanning algorithms for processor arrays. Internal report of the Pattern Recognition Group, Departement of Applied Physics, Delft University of Technology.
Buurman J., Duin R.P.W.; Proposal for a fast scanning processor array architecture. Internal report of the Pattern Recognition Group, Departement of Applied Physics, Delft University of Technology.
Davis R., Thomas D.; Systolic array chip matches the pace of high speed processing. Electronic design, pp. 207–218, 31 Oct. 1984.
Dekker S.T., Jonker P.P., Groen F.C.A.; Distance transforms with data flow techniques. To be published in Proc. of the 6th Aachen symposium on signal theory, ASST’87, Sept 9–12, 1987.
Duff, M.J.B.; CLIP4. In: Fu, K.S. and Tadao Ichikawa (eds.), Special Computer Architectures for Pattern Processing, CRC Press, Boca Raton, Florida, USA, 1982, pp. 65–86.
Duin R.P.W., Haringa H., Zeelen R.; Fast percentile filtering. Pattern Recognition letters 4 (1986), pp 269–272.
Duin R.P.W., Haringa H., Zeelen R.; A hardware design for fast 2-D percentile filtering. Proceedings SPIE conf. Vol. 596 pp. 36–40, 1985.
Duin R.P.W., Jonker P.P.; Processor arrays versus pipelines for cellular logic image operations, In: Proceedings Signal processing III: theories and applications. Amsterdam North Holland, 1986, pp. 1339–1343.
Duin R.P.W., Gerritsen F.A.; The Delft Image Analysis Laboratory. In: Kittler J., and Duff M.J.B., Image Processing System Architectures. Research Studies Press LTD. UK, 1985, Ch. 8.
Gerritsen F.A., Aardema L.A.; Design and use of DIP-1. Pattern Recognition, Vol. 14, Nos. 1-6, pp. 319–330, 1981.
Granlund G.H., Arvidsson J.B.; Computer architectures for image processing. Proceedings of the 4th Scandinavian Conference on image analysis. Trondheim, Norway, June 17-20 1985.
Groen F.C.A., Foster N.J., A fast algorithm for Cellular Logic operations on sequential machines, Pattern recognition letters, vol. 2, 1984, pp 333–338.
Groen F.C.A., Ekkers R.J., de Vries R.; Image processing with personal computers. To be Published in Proceedings of the IEEE-ASSP & EURASIP Fifth Workshop on Multidimensional Signal Processing, September 14-16, 1987, Noordwijkerhout, The Netherlands. North Holland.
Hilditch C.J.; Linear Skeletons from square cupboards. In: Meltzer B., Mitchie D. (Eds.). Machine Intelligence Vol. 4. (1969) University Press Edingburgh, 404–420.
Huang T.S., Yang G.J., Tang C.Y.; A fast two-dimensional median filtering algorithm, IEEE trans on ASSP, Vol ASSP-27, no 1. february 1979, pp. 13–18.
Iwashita M., et al.; A data driven VLSI image processor (IMPP). In: Uhr L., Preston Jr. K., Levialdi S., Duff M.B.J., Evaluation of Multicomputer for Image Processing. Academic Press Inc., Orlando Florida USA, 1986.
Kraaijveld M.A., Jonker P.P., Nouta R., Duin R.P.W.; The VLSI realisation of a binary-image processor, In Proceedings Signal Processing III: theories and applications. Amsterdam, North-Holland, 1986, pp. 1231–1234.
Kung H.T.; Why systolic Architectures?. IEEE Computer, Vol. 12, no 1, January 1982.
Kuwahara M., Hachimura K., Eiho S., Kinoshita M.; Processing of RI-angiocardiographic images. In: Digital Processing of Biomedical images. K. Preston Jr., M. Onoe (Eds.), Plenum Press, New York, 1976, pp. 187–202.
Piper J.; Efficient implementation of skeletonisation using interval coding. Pattern Recognition Letters 3, 1985, pp. 389–397.
Pratt W.K., Leonard P.F.; Review of Machine Vision Architectures. Proceedings SPIE Conf Vol 755.
Preston K., Duff M.J.B.; Modern Cellular Automata, Theory and Applications. Plenum Press, New York, 1984
Preston K., Benchmark Results, The Abingdon Cross, In: Uhr L., Preston Jr. K., Levialdi S., Duff M.B.J., Evaluation of Multicomputer for Image Processing. Academic Press Inc., Orlando Florida USA, 1986.
Siegel S.; VME building blocks make image processing a snap. Electronics Test, Octobre 1985.
Smith W.W., Sullivan P.; Systolic array chip matches the pace of high speed processing, electronic Design, October 31,1984, pp 207–209
Thissen F. L.; The Philips modular picture acquisition and processing system — PAPS. Proceedings of the 5th Intl. Conf. on Robot vision and sensory controls, 29–31 October 1985, Amsterdam, pp. 587–598.
van Vliet L, Verwer B.J.; A fast contour processing method for binary neighbourhood operations. Internal report of the Pattern Recognition Group, Departement of Applied Physics, Delft University of Technology. To be published.
Watson I, Gurd J.R., A practical dataflow Computer, IEEE Computer, Vol. 15, no.2, February 1982, p 51.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1988 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Groen, F.C.A., Jonker, P.P., Duin, R.P.W. (1988). Hardware Versus Software Implementations of Fast Image Processing Algorithms. In: Jain, A.K. (eds) Real-Time Object Measurement and Classification. NATO ASI Series, vol 42. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-83325-0_5
Download citation
DOI: https://doi.org/10.1007/978-3-642-83325-0_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-83327-4
Online ISBN: 978-3-642-83325-0
eBook Packages: Springer Book Archive