Silicon Implementation of Multiprocessor Pyramid Architecture

  • Franco Maloberti
Conference paper
Part of the NATO ASI Series book series (volume 25)


Pyramid architecture are very promising for parallel image processing [1]. Good interprocessor communication is supported by the pyramid topology and image analysis at different resolution level is allowed. These and other advantages have stimulated the activity of several research groups and now, after theoretical studies, many of then are engaged upon the practical implementation of multiprocessor pyramid architectures. All the realizations must be based on a custom integrated circuit that realizes a defined fractional part of the pyramid.


Power Dissipation Chip Area VLSI Circuit Programmable Logic Array Instruction Decoder 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • Franco Maloberti
    • 1
  1. 1.Department of ElectronicsUniversity of PaviaPaviaItaly

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