Abstract
This paper presents the GIPSi processor array which is a programmable VLSI chip designed for local linear and non-linear image filtering algorithms. A first section introduces the GIPSi approach. Then the parallel SIMD architecture is described followed by a section about implemented algorithms. Special emphasis is laid on a rank order filter algorithm which has been adapted to the SIMD architecture. It follows a section concerning the VLSI implementation of the GIPSi system and some conclusions.
This work has been done in cooperation with TU Hamburg Harburg, Technische Informatik I.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Stanley R. Sternberg. Biomedical Image Processing. Computer, Seite 22–34, January 1983.
Anthony P. Reeves. SURVEY Parallel Computer Architectures for Image Processing. Computer Vision, Graphics and Image Processing, 25:68–88, 1984.
S. Y. Kung. VLSI Array Processors Prentice Hall, Englewood Cliffs, NY, 1988.
A.L. Fisher and P.T. Highnam. Real-Time Image Processing on Scan Line Array Processors. IEEE Workshop on Computer Architecture for Pattern Analysis and Image Database Management, Miamy, FL, 1985.
S.S. Wilson. One Dimensional SIMD Architectures — The AIS-5000. In S. Levialdi, editor, Multicomputer Vision, Academic Press, 1988.
H. Miyaguchi, H. Krasawa, S. Watanabe, J. Childers, P. Reinecke and M. Becker. Digital TV with Serial Video Processor. IEEE Transactions on Consumer Electronics, Vol. 36, No. 3, August 1990;
K. Chen and C. Svenson. A 512-Processor Array Chip for Video/Image Processing. In H. Burkhardt, Y. Neuvo and J.C. Simon, editors, From Pixels to Feaiures II, Parallelism in Image Processing. ESPRIT BRA 3035 Workshop, Bonas, September 1990
N. Yamashita, T. Kimura, Y. Fujita, Y. Aimoto, T. Manabe, S. Okazaki, K. Nakamura, and M. Yamashina. A 3.84GIPS Integrated Memory Array Processor LSI with 64 Processing Elements and 2Mb SRAM. ISSCC94, Session 15, Psaper FA 15.2, 1994
B. Lang. Self Arbitrating Elements for Modelling Systolic Dataflow in Field Programmable Gate Arrays. In Proceedings GI/ITG Workshop Anwenderprogrammierbare Schaltungen, Karlsruhe, 1994. Available via Internet: itp://www.til.tu-harburg.de/pub/papers/la:ka.psitp://www.til.tu-harburg.de/pub/papers/la:ka.ps.
B. Lang. The GIPSI System. Internal Report No. 9/94, Technische Universität Hamburg- Harburg, Technische Informatik I, 1994.Available via Internet: ftp://www.til.tu-harburg.de/pub/papers/la:gipsi.ps
Q. Gu and M.N.S. Swamy. A Binary Logic Synthesis Approach to the Bit-Level Implementation of Generalized Rank-Order Filters. 1992 IEEE Intl. Symposium on Circuits and Systems. Vol. 1, San Diego, CA, May 10–13, 1992.
D. E. Knuth. The Art of Computer Programming, Vol. 3: Sorting and Searching, Addison Wesley, 1973.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1995 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lang, B., Troike, M. (1995). A VLSI system for linear and non-linear local image filtering. In: Sagerer, G., Posch, S., Kummert, F. (eds) Mustererkennung 1995. Informatik aktuell. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-79980-8_22
Download citation
DOI: https://doi.org/10.1007/978-3-642-79980-8_22
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-60293-4
Online ISBN: 978-3-642-79980-8
eBook Packages: Springer Book Archive