Abstract
The paper describes the hardware and software components of the Intel Paragon XP/S system, a distributed memory scalable multicomputer. The Paragon processing nodes, which are based on the Intel i860 XP RISC processor, are connected by a two-dimensional mesh with high bandwidth. This new interconnection network and the new operating system are the main differences between the Paragon and its predecessor, the iPSC/860 with its hypercube topology. The paper first gives an overview of the Paragon system architecture, the node architecture, the interconnection network, I/O interfaces, and peripherals. The second part outlines the Paragon OSF/1 operating system and the program development environment including programming models, compilers, application libraries, and tools for parallelization, debugging, and performance analysis.
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References
Anderson, E., et al.: LAPACK User’s Guide. Philadelphia, SIAM, 1992
Applied Parallel Research: FORGE 90, Version 8.0, User’s Guide. 1992
Dally, W.J., Seitz, C.L.: The Torus Routing Chip. J. Distributed Computing, Vol. 1, No. 3 (1986) 187 - 196
Esser, R., Knecht, R. (eds.): Applications on KFA’s Intel iPSC/860. Interner Bericht, KFA-ZAM-IB-9218, Forschungszentrum Jülich, 1992
High Performance Fortran Forum: High Performance Fortran Language Specification (DRAFT), Version 0. 4. Rice University, Houston TX, 1992
IEEE STD 1149.1-1990: IEEE Standard Test Access Port and Boundary Scan Architecture.
Intel Corporation: i860 Microprocessor Family Programmer’s Reference Manual. Order No. 240875-002, 1992
Intel Supercomputer Systems Division: iPSC/860 Software Resource Catalog. Beaverton OR, December 1991
Lee, K.: On the Floating Point Performance of the i860 Microprocessor. Int. J. High Speed Computing, Vol. 4, No. 4 (1992) 251–267
Li, K.: Shared Virtual Memory on Loosely-coupled Multiprocessors. PhD Thesis, Yale University, Technical Report YALEU-RR-492, October 1986
Loepere, K.: Mach 3 Kernel Principles, Open Software Foundation and Carnegie Mellon University, 1992
Mlynski-Wiese, A.: Die Architektur der Prozessorfamilie i860. Interner Bericht KFA-ZAM-IB-9214, Forschungszentrum Jülich, 1992
Ni, L.M., McMinley, P.K.: A Survey of Wormhole Routing Techniques in Direct Networks. IEEE Computer, February 1993, 62–76
OSF/1 Operating System, User’s Guide. Open Software Foundation, Prentice Hall, 1992
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© 1993 Springer-Verlag Berlin Heidelberg
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Esser, R., Knecht, R. (1993). Intel Paragon XP/S - Architecture and Software Environment. In: Meuer, HW. (eds) Supercomputer ’93. Informatik aktuell. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-78348-7_13
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DOI: https://doi.org/10.1007/978-3-642-78348-7_13
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-56948-0
Online ISBN: 978-3-642-78348-7
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