Acceleration of RAM-Tests with Associative Pattern Recognition Methods

Abstract

In this paper we describe a new concept for testing large scale static RAMs. Generally a RAM consists of storage cells which are grouped in rectangular fields on the memory chip. If the cells in one field store the same information (0 or 1) and no faulty cells exist in the field, we can interpret the field as a homogeneous field. But we have an inhomogeneous field, if there are some faulty cells with dual informations (1 or 0). This interpretation of faulty cells allows to define the test problem as a pattern recognition problem. Thus it can be treated with parallel search operations and corresponding search algorithms normally used in associative memory systems. In order to detect and localize existing faults the used test patterns are adapted after each evaluation step in algorithmic manner. Therefore the test patterns cannot be generated with classical methods like the table-look-up-method or predefined runtime generation. This new way to deal with SRAM-tests enables procedures to be developped which provide a drastic reduction of testpatterns and testing time. This paper describes exemplarily the basics of using flag-oriented associative structures combined with parallel search algorithms to accelerate SRAM-tests. The basic algorithm will be demonstrated with test procedures replacing test algorithms of both linear and quadratic complexity.