Abstract
We present an approximation algorithm for the performance analysis of a shared buffer ATM switch architecture. The arrival process to each input port of the ATM switch is assumed to be bursty and it is modelled by an Interrupted Poisson Process. Comparisons against simulation showed that the approximation algorithm has a good error-level.
Supported in part by DARPA under grant no. DAEA18-90-C-0039 and by the National Science Foundation under grant no. CCR-87-02258.
On a sabbatical leave of absence from Sophia Univ., Tokyo, Japan.
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© 1991 Springer-Verlag Berlin Heidelberg
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Yamashita, H., Perros, H.G., Hong, SW. (1991). An Approximation Analysis of a Shared Buffer ATM Switch Architecture under Bursty Arrivals. In: Pujolle, G. (eds) High-Capacity Local and Metropolitan Area Networks. NATO ASI Series, vol 72. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-76484-4_19
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DOI: https://doi.org/10.1007/978-3-642-76484-4_19
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