Advertisement

Robotics Vector Processor Architecture for Real-Time Control

  • David E. Orin
  • P. Sadayappan
  • Y. L. C. Ling
  • K. W. Olson
Part of the NATO ASI Series book series (volume 66)

Abstract

This paper proposes a restructurable architecture based on a VLSI Robotics Vector Processor (RVP) chip. It is specially tailored to exploit parallelism in the low-level matrix/vector operations characteristic of the kinematics and dynamics computations required for real-time control. The RVP is comprised of three tightly synchronized 32-bit floating-point processors to provide adequate computational power. Besides adder and multiplier units in each processor, the RVP contains a triple register-file, dual shift network and dual high-speed input/output channels to satisfy the storage and data movement demands of the computations targeted. Efficiently synchronized multiple-RVP configurations, that may be viewed as Variable-Very-Long-Instruction-Word (V2LIW) architectures, can be constructed and adapted to match the computational requirements of specific robotics computations. The use of the RVP is illustrated through a detailed example of the Jacobian computation, demonstrating good speedup over conventional microprocessors even with a single RVP. The RVP has been developed to be implementable on a single VLSI chip using a 1.2 μm CMOS technology, so that a single-board multiple-RVP system may be targeted for use on a mobile robot.

Keywords

Clock Cycle Task Graph Vector Operation Host Processor Robot Kinematic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    D.J. Kriegman, D.M. Siegel, S. Narasimhan, J.M. Hollerbach and G.E. Gerpheide, “Computational Architecture for the Utah/MIT Hand,” Proc. of the IEEE International Conference on Robotics and Automation, pp. 918–924, St. Louis, MO, March 1985.Google Scholar
  2. [2]
    J.B. Chen, R.S. Fearing, B.S. Armstrong and J.W. Burdick, “NYMPH: A Multiprocessor for Manipulation Applications,” Proc. of the IEEE International Conference on Robotics and Automation. Vol. 3, pp. 1731–1736, San Francisco, CA, April 1986.Google Scholar
  3. [3]
    R.B. McGhee, D.E. Orin, D.R. Pugh and M.R. Patterson, “A Hierarchically-Structured System for Computer Control of a Hexapod Walking Machine,” Proc. of Symposium on Theory and Practice of Robots and Manipulators. Udine, Italy, June 1984.Google Scholar
  4. [4]
    J.Y.S. Luh and C.S. Lin, “Scheduling of Parallel Computation for a Computer-Controlled Mechanical Manipulator,” IEEE Transactions on Systems. Man and Cybernetics. Vol. SMC-12, pp. 214–234, March 1982.CrossRefGoogle Scholar
  5. [5]
    J. Barhen, “Robot Inverse Dynamics on a Concurrent Computation Ensemble,” Proc. of 1985 ASME International Conference on Computers in Engineering. Vol. 3, pp. 415–429, Boston, MA, August 1985.Google Scholar
  6. [6]
    R. Nigam and C.S.G. Lee, “A Multiprocessor-Based Controller for the Control of Mechanical Manipulators,” IEEE Journal of Robotics and Automation. Vol. RA-1, No. 4, pp. 173–182, Dec. 1985.CrossRefGoogle Scholar
  7. [7]
    C.S.G. Lee and P.R. Chang, “Efficient Parallel Algorithm for Robot Inverse Dynamics Computation,” IEEE Transactions on Systems. Man and Cybernetics. Vol. SMC-16, No. 4, pp. 532–542, July/August 1986.CrossRefGoogle Scholar
  8. [8]
    L.H. Lathrop, “Parallelism in Manipulator Dynamics,” International Journal of Robotics Research. Vol. 4, No. 2, pp. 80–102, Summer 1985.CrossRefGoogle Scholar
  9. [9]
    D.E. Orin, K.W. Olson and H.H. Chao, “Systolic Architectures for Computation of the Jacobian for Robot Manipulators,” in Computer Architectures for Robotics and Automation, pp. 39–67, Edited by J.H. Graham, Gordon and Breach Science Publishers, New York, 1987.Google Scholar
  10. [10]
    M. Amin-Javaheri and D.E. Orin, “A Systolic Architecture for Computation of the Manipulator Inertia Matrix,” Proc. of the IEEE International Conference on Robotics and Automation. Vol. 2, pp. 647–653, Raleigh, NC, April 1987.Google Scholar
  11. [11]
    Y. Wang and S.E. Butner, “A New Architecture for Robot Control,” Proc. of the IEEE International Conference on Robotics and Automation. Vol. 2, pp. 664–670, Raleigh, NC, April 1987.Google Scholar
  12. [12]
    S.S. Leung and M.A. Shanblatt, “Real-Time DKS on a Single Chip,” IEEE Journal of Robotics and Automation. Vol. RA-4, No. 3, pp. 281–290, August 1987.CrossRefGoogle Scholar
  13. [13]
    H.H. Chao, Parallel/Pipeline VLSI Computing Structures for Robotics Applications. Ph. D. dissertation, The Ohio State University, Columbus, OH, June 1985.Google Scholar
  14. [14]
    Y.T. Tsai and D.E. Orin, “A Strictly Convergent Real-Time Solution for Inverse Kinematics of Robot Manipulators.” Journal of Robotic Systems. Vol. 4, No. 4, pp. 477–501, 1987.CrossRefGoogle Scholar
  15. [15]
    C.S.G. Lee and P.R. Chang, “A Maximum Pipelined CORDIC Architecture for Inverse Kinematic Position Computation,” IEEE Journal of Robotics and Automation. Vol. RA-3, No. 5, pp. 445–458, Oct. 1987.CrossRefGoogle Scholar
  16. [16]
    Y.L.C. Ling, K. Olson, D.E. Orin and P. Sadayappan, “A Layered Restructurable VLSI Architecture for Robotics Control,” Proc. of 1987 IEEE International Conference on Computer Design, pp. 267–272, Port Chester, NY, October 1987.Google Scholar
  17. [17]
    K. W. Lilly and D.E. Orin, “Multiprocessor Implementation of Dynamic Control Schemes for Robot Manipulators,” Proceedings of 1986 ASME International Computers in Engineering Conference. Vol. 1, pp. 53–59, Chicago, IL, July 1986.Google Scholar
  18. [18]
    D.E. Orin and W.W. Schrader, “Efficient Computation of the Jacobian for Robot Manipulators,” International Journal of Robotics Research. Vol. 3, No. 4, pp. 66–75, Winter 1984.CrossRefGoogle Scholar
  19. [19]
    K. Hwang and F. Briggs, Computer Architecture and Parallel Processing. McGraw-Hill, New York, 1984.MATHGoogle Scholar
  20. [20]
    H.T. Kung. “Why Systolic Architectures?.” IEEE Computer. Vol. 15, No. 1,pp. 37–46, Jan. 1982.CrossRefGoogle Scholar
  21. [21]
    J.A. Fisher, “Very Long Instruction Word Architectures and the ELI-512,” Proceedings of 10th Annual Symposium on Computer Architecture, pp. 140–150, Stockholm, Sweden, June 1983.Google Scholar
  22. [22]
    Y.L.C. Ling, Layered Multiprocessor Architecture Design in VLSI for Real-Time Robotic Control. Ph. D. dissertation, The Ohio State University, Columbus, OH, Dec. 1986.Google Scholar
  23. [23]
    M.W. Walker and D.E. Orin, “Efficient Dynamic Computer Simulation of Robotic Mechanisms,” ASME Journal of Dynamic Systems. Measurement, and Control. Vol. 104, pp. 205–211, September 1982.MATHCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1991

Authors and Affiliations

  • David E. Orin
    • 1
  • P. Sadayappan
    • 2
  • Y. L. C. Ling
    • 3
  • K. W. Olson
    • 1
  1. 1.Department of Electrical EngineeringThe Ohio State UniversityColumbusUSA
  2. 2.Department of Computer & Information ScienceThe Ohio State UniversityColumbusUSA
  3. 3.High Tech CenterBoeing Electronics Co.BellevueUSA

Personalised recommendations