Abstract
This paper proposes a restructurable architecture based on a VLSI Robotics Vector Processor (RVP) chip. It is specially tailored to exploit parallelism in the low-level matrix/vector operations characteristic of the kinematics and dynamics computations required for real-time control. The RVP is comprised of three tightly synchronized 32-bit floating-point processors to provide adequate computational power. Besides adder and multiplier units in each processor, the RVP contains a triple register-file, dual shift network and dual high-speed input/output channels to satisfy the storage and data movement demands of the computations targeted. Efficiently synchronized multiple-RVP configurations, that may be viewed as Variable-Very-Long-Instruction-Word (V2LIW) architectures, can be constructed and adapted to match the computational requirements of specific robotics computations. The use of the RVP is illustrated through a detailed example of the Jacobian computation, demonstrating good speedup over conventional microprocessors even with a single RVP. The RVP has been developed to be implementable on a single VLSI chip using a 1.2 μm CMOS technology, so that a single-board multiple-RVP system may be targeted for use on a mobile robot.
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© 1991 Springer-Verlag Berlin Heidelberg
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Orin, D.E., Sadayappan, P., Ling, Y.L.C., Olson, K.W. (1991). Robotics Vector Processor Architecture for Real-Time Control. In: Lee, C.S.G. (eds) Sensor-Based Robots: Algorithms and Architectures. NATO ASI Series, vol 66. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-75530-9_11
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DOI: https://doi.org/10.1007/978-3-642-75530-9_11
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