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Hierarchical Layout and Checking

  • Kurt Pollmann
  • Rainer Zühlke

Abstract

The VLSI chip images are built from a few building elements: A horizontal I/O cell, a vertical I/O cell and an ‘image module’ for the internal chip. Figure 192 shows that this image module is 1 horizontal I/O position high and 2 vertical I/O positions wide. It contains 40 positions for the placement of logic books. The power distribution is contained in this module. Any size of chips could be constructed from these elements. The 12.7 mm × 12.7 mm chip size has 38×65 = 2470 modules; the smaller 9.4 mm × 9.4 mm STC chip has an 24×41 = 984 array. This regularity allows to generate shapes of books and wires on smaller working images and move them correctly on the real chip. The working chips must support the largest partition and not exceed the limits of the physical design system, for example the wiring program limits.

Keywords

Power Distribution Logic Book Large Partition Logical Check Cache Directory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • Kurt Pollmann
  • Rainer Zühlke

There are no affiliations available

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