The processing unit (CPU) chip is the center piece of the Capitol Chip Set. Its implementation is very similar to the IBM 4361 and IBM 9370–90 CPUs. We know from past experience, that these implementations feature a very good trade-off between performance and number of circuits and arrays employed. However, they are bipolar realisations. In order to translate them into a CMOS realisation, and accommodate the design within the restrictions of the 12.7 x 12.7 millimeter chips and the corresponding packaging technology, a significant redesign activity was required.
KeywordsCache Line Operation Register Logic Design Main Store Exceptional Condition
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