Embedded Array Macros

  • Klaus Helwig
  • Heinrich Lindner

Abstract

The data flow of the MMU-chip as described in “2.4.3 MMU Chip Data Flow” on page 56 requires four array macros (arrays): Cache (high performance buffer memory), TLB (Translation-Lookaside Buffer for dynamic address translation), CD (Cache Directory), and Key Store. These four array macros are integrated together with the MMU control logic on a single chip (see Figure 141). Plate 8 shows a part of an MMU wafer.

Keywords

Coupler AITC 

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Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • Klaus Helwig
  • Heinrich Lindner

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