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Master Image Chip

  • Helmut Schettler

Abstract

Structured (non-customized) chip designs use either the gate array or the master image approach. A gate array chip is divided into many cells of fixed size. Each cell contains the same logic gate (e. g. 3-way NAND gate). Multiple designs are implemented by a unique wiring of the basic cells with 2 (or more) layers of metal, using an identical underlaying silicon structure.

Keywords

Logic Gate Chip Area Automatic Design System Master Image VLSI Chip 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • Helmut Schettler

There are no affiliations available

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