Structured (non-customized) chip designs use either the gate array or the master image approach. A gate array chip is divided into many cells of fixed size. Each cell contains the same logic gate (e. g. 3-way NAND gate). Multiple designs are implemented by a unique wiring of the basic cells with 2 (or more) layers of metal, using an identical underlaying silicon structure.
KeywordsLogic Gate Chip Area Automatic Design System Master Image VLSI Chip
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