Summary
This paper discusses architectures for realization of block matching algorithms with emphasis on highly concurrent systolic array processors. A three step mapping methodology for systolic arrays known from the literature is applied to block matching algorithms. Examples of 2-dimensional and 1-dimensional systolic arrays are presented. The needed array size, the transistor count and the maximum frame rate for processing video telephone and TV signals have been estimated.
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© 1989 Springer-Verlag Berlin Heidelberg
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Pirsch, P., Komarek, T. (1989). Systolic Arrays for Block Matching Algorithms. In: Linkwitz, K., Hangleiter, U. (eds) High Precision Navigation. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-74585-0_26
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DOI: https://doi.org/10.1007/978-3-642-74585-0_26
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-74587-4
Online ISBN: 978-3-642-74585-0
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