Abstract
This paper presents an analysis of an N×N, internally non-blocking packet switch with two different priority classes. The analysis extends methods developed in recent publications for systems with a single priority class. A possible application of this work is in the analysis of integrated packet switches that support both voice and data traffic with different priorities. The switch is operated in a slotted fashion, and the probabilities of packet arrival in a time slot are distinct for the two priority classes. Low priority packets can be queued. High priority packets are cleared from the system in case of unsuccessful transmission through the switch. The results developed in the paper provide performance measures such as blocking probabilities and average delays. Expressions for system stability and total throughput are also studied in terms of both high and low priority traffic loads. Numerical examples illustrate the results.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Bibliography
C.-L. Wu and T.-Y. Feng, editor. Tutorial: Interconnection Networks for Parallel and Distributed Processing IEEE Computer Society Press, 1984. (IEEE Cat. # EH0217–0).
H. Ahmadi, W. Denzel, C. A. Murphy, and E. Port, “A High Performance Switch Fabric for Integrated Circuit and Packet Switching,” Proc. of the 1988 Infocom Conference (INFOCOM’88 Cont. Rec.), pp. 9–18, 1988.
D. P. Bhandarkar, “Analysis of Memory Interference in Multiprocessors,” IEEE Trans. Comp., vol. C-24, no. 9, pp. 897–908, September 1975.
J. S.-C. Chen and R. Guérin, Input Queueing of an Internally Non-Blocking Packet Switch with Two Priority Classes, IBM Research Division, RC Report 13911 (#62487), October 1988.
J. S.-C. Chen and R. Guérin, Performanc%Study of an Integrated Packet Switch with with Two Priority Classes, IBM Research Division, RC Report 13774 (#61720), May 1988.
J. S.-C. Chen and R. Guérin, “Input Queueing of an Internally Non-Blocking Packet Switch with Two Priority Classes,” To be presented at INFOCOM’89, 1989.
D. M. Dias and J. R. Jump, “Analysis and Simulation of Buffered Delta Networks,” IEEE Trans. Comp., vol. C-30, no. 4, pp. 273–282, April 1981.
A. E. Eckberg and T.-C. Hou, “Effects of Output Buffer Sharing on Buffer Requirements in an ATDM Packet Switch,” Proc. of the 1988 Infocom Conference (INFOCOM’88 Conf. Rec.), pp. 459–465, 1988.
K. Y. Eng, M. G. Hluchyj, and Y.-S. Yeh, “A Knockout Switch for Variable-Length Packets,” IEEE Jour. Selec. Areas Commun., vol. SAC-5, no. 9, pp. 1426–1435, December 1987.
G. Hebuterne, “STD Switching in an ATD Environment,” Proc. of the 1988 Infocom Conference (INFOCOM’88 Conf. Rec), pp. 449–458, 1988.
M. C. Hluchyj and M. J. Karol, “Queueing in Space-Division Packet Switching,” Proc. of the 1988 Infocom Conference (INFOCOM’88 Conf. Rec.), pp. 334–343, 1988.
A. Huang and S. Knauer, “STARLITE: A Wide-band Digital Switch,” Proc. of the 1984 Globecom Conference (GLOBECOM’84 Conf. Rec.), vol. 1, pp. 5.3.1–5.3. 5, Atlanta, Georgia, November 1984.
J. Y Hui and E. Arthurs, “A Broadband Packet Switch for Integrated Transport,” IEEE J. Selec. Areas Commun., vol. SAC-5, no. 8, pp. 1264–1273, October 1987.
Y.-C. Jenq, “Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network,” IEEE J. Select. Areas Commun., vol. SAC-1, no. 6, pp. 1014–1021, December 1983.
M. J. Karol and M. C. Hluchyj, “Using a Packet Switch for Circuit-Switched Traffic: A Queueing System with Periodic Input Traffic,” Proc. of the 1987 Infocom Conference (INFOCOM’87 Conf. Rec.), pp. 1677–1682, 1987.
M. J. Karol, M. C. Hluchyj, and S. P. Morgan, “Input Vs. Output Queueing on a Space-Division Packet Switch,” IEEE Trans. Commun., vol. COM-35, no. 12, pp. 1347–1356, December 1987.
C. P. Kruskal and M. Snir, “The Performance of Multistage Interconnection Networks for Multiprocessors,” IEEE Trans. Comput., vol. C-32, no. 12, pp. 1091–1098, December 1983.
B. N. W. Ma and J. W. Mark, “Performance Analysis of Burst Switching for Integrated Voice/Data Networks,” IEEE Trans. Commun., vol. COM-36, no. 3, pp. 282–297, March 1988.
S. Nojima, E. Tsutsui, H. Fukuda, and M. Hashimoto, “Integrated Services Packet Network Using Bus Matrix Switch,” IEEE J. Select. Areas Commun., vol. SAC-5, no. 8, pp. 1284–1292, October 1987.
J. K Patel, “Performance of Processor-Memory Interconnections for Multiprocessors,” IEEE Trans. Computers, vol. C-30, no. 10, pp. 771–780, October 1981.
J. S. Turner and L. F. Wyatt, “A Packet Network Architecture for Integrated Services,” Proc. of the 1983 Globecom Conference (GLOBECOM’83 Conf. Rec), pp. 45–50, November 1983.
Y.-S. Yeh, M. G. Hluchyj, and A. S. Acampora, “The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching,” IEEE J. Select. Areas Commun., vol. SAC-5, no. 8, pp. 1274–1283, October 1987.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1989 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Chen, J.SC., Guérin, R. (1989). Performance Study of an Integrated Packet Switch with Two Priority Classes. In: Kühn, P.J. (eds) Kommunikation in verteilten Systemen. Informatik-Fachberichte, vol 205. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-74570-6_28
Download citation
DOI: https://doi.org/10.1007/978-3-642-74570-6_28
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-50893-9
Online ISBN: 978-3-642-74570-6
eBook Packages: Springer Book Archive