Skip to main content

Trench Isolation Schemes for Bipolar Devices: Benefits and Limiting Aspects

  • Chapter
Ultra-Fast Silicon Bipolar Technology

Part of the book series: Springer Series in Electronics and Photonics ((SSEP,volume 27))

Abstract

This chapter gives a review of benefits and limiting aspects of the trench isolation techniques for bipolar devices. The most sophisticated trench isolation techniques have realized not only a high packing density but also reduced collector-substrate, wiring-substrate and base- collector parasitic capacitances. By using these techniques, high performance bipolar devices such as ultra-high-speed ECL RAMs, gate arrays and microprocessors have been fabricated. However, crystalline defects caused by trench structures continue to pose serious problems. Trench isolation techniques are still in the process of development, and it seems that there is no apparent limiting aspect unless the trench width exceeds the filler material width necessary to sustain enough breakdown voltage.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. J.A. Bondur, H.B. Pogge: Method for forming isolated regions of silicon utilizing reactive ion etching, U.S. Patent 4104086, Aug. 1978

    Google Scholar 

  2. H. Goto, T. Takada, R. Abe, Y. Kawabe, K. Oami, M. Tanaka: An isolation technology for high performance bipolar memories-IOP-II. IEDM Techn. Dig. (1982) pp.58–61

    Google Scholar 

  3. A. Hayasaka, Y. Tamaki, M. Kawamura, K. Ogiue, S. Ohwaki: U-groove isolation technique, for high speed bipolar VLSIs. IEDM Techn. Dig. (1982) pp.62–65

    Google Scholar 

  4. G.C. Schwartz, P.M. Schaible: Reactive ion etching of silicon. J. Vac. Sci. Technol. 16, 410–413 (1979)

    Article  CAS  Google Scholar 

  5. H.B. Pogge, J.A. Bondur, P.J. Burkhardt: Reactive ion etching of silicon with Cl2/Ar(i). J. Electrochem. Soc. 130, 1592–1597 (1983)

    Article  CAS  Google Scholar 

  6. H. Goto, T. Takada, K. Nawata, Y. Kanai: A new isolation technology for bipolar VLSI logic (IOP-L). Symp. on VLSI Technology Techn. Dig. (1985) pp.42–43

    Google Scholar 

  7. H. Sakai, K. Kikuchi, S. Kameyama, M. Kajiyama, T. Komeda: A trench isolation technology for high-speed and low-power dissipation bipolar LSIs. Symp. on VLSI Technology, Techn. Dig. (1987) pp. 17–18

    Google Scholar 

  8. T. Shibata, R. Nakayama, K. Kurosawa, S. Onga, M. Konaka, H. Iizuka: A simplified BOX (Buried OXide) isolation technology for megabit dynamic memories. IEDM Techn. Dig. (1983) pp.27–30

    Google Scholar 

  9. D.D. Tang, P.M. Solomon, T.H. Ning, R.D. Isaac, R.E. Burger. 1.25μm deep-groove-isolated self-aligned ECL circuits. ISSCC Techn. Dig. (1982) pp.242–243

    Google Scholar 

  10. S.F. Chu, G.R. Srinivasan, H. Bhatia, B.M. Kemlage, F. Barson, J. Mauer, J. Riseman: A self-aligned bipolar transistor. VLSI Science and Technology, Techn. Dig. (1982) pp.306–314

    Google Scholar 

  11. Y. Tamaki, T. Shiba, N. Honma, S. Mizuo, A. Hayasaka: New U-groove isolation technology for high-speed bipolar memory. Symp. on VLSI Technology, Techn. Dig. (1983) pp.24–25

    Google Scholar 

  12. D.D. Tang, G.P. Li, CT. Chuang, D. Danner, M.B. Ketchen, J. Mauer, M. Smyth, M. Manny, J.D. Cressler, B. Ginsberg, E. Petrillo, T.H. Ning, C.C. Hu, H.S. Park: 73ps Si bipolar ECL circuits. ISSCC Techn. Dig. (1986) pp. 104–105

    Google Scholar 

  13. G.P. Li, T.H. Ning, C.T. Chuang, M.B. Ketchen, D.D. Tang, J. Mauer: An advanced high-performance trench-isolated self-aligned bipolar technology. IEEE Trans. ED-34, 2246–2253 (1987)

    CAS  Google Scholar 

  14. M. Vora, Y.L. Ho, S. Bhamre, F. Chien, G. Bakker, H. Hingarh, C. Schmitz: A sub-100 picosecond bipolar ECL technology. IEDM Techn. Dig. (1985) pp.34–37

    Google Scholar 

  15. H. Sadamatsu, M. Inoue, A. Matsuzawa, A. Kanda, H. Shimoda: New self-aligned complementary bipolar transistors using selective-oxidation mask. IEDM Techn. Dig. (1984) pp.753–756

    Google Scholar 

  16. K. Ueno, H. Goto, E. Sugiyama, H. Tsunoi: A sub-40ps ECL circuit at a switching current of 1.28mA. IEDM Techn. Dig. (1987) pp.371–374

    Google Scholar 

  17. K. Ooami, M. Tanaka, Y. Sugo, R. Abe, T. Takada: A 3.5ns 4kb ECL RAM, ISSCC Techn. Dig. (1983) pp.114–115

    Google Scholar 

  18. K. Toyoda, M. Tanaka, H. Isogai, C. Ono, Y. Kawabe, H. Goto: A 15ns 16kb ECL RAM with a PNP load cell. ISSCC Techn. Dig. (1983) pp.108–109

    Google Scholar 

  19. Y. Okajima, K. Tokuda, K. Awaya, K. Tanaka, Y. Nakamura: 64 kb ECL RAM with redundancy, ISSCC Techn. Dig. (1985) pp.48–49

    Google Scholar 

  20. Y. Sugo, M. Tanaka, Y. Mafune, T. Takeshima, S. Aihara, K. Tanaka: An ECL 2.8ns 16k RAM with 1.2k logic gate array. ISSCC Techn. Dig. (1986) pp.256–257

    Google Scholar 

  21. T. Awaya, K. Toyoda, O. Nomura, Y. Nakaya, K. Tanaka, H. Sugawara: A 5ns access time 64 kb ECL RAM. ISSCC Techn. Dig. (1987) pp.130–131

    Google Scholar 

  22. H. Suzuki, T. Akiyama, K. Ueno: A 1.6GHz low power silicon dual modulus prescaler IC. IEDM Techn. Dig. (1984) pp.682–685

    Google Scholar 

  23. K. Yamaguchi, K. Kanetani, H. Todokoro, T. Nakano, K. Akimoto, K. Ogiue: An ECL 4k-bit bipolar RAM with an effective access time of 2.5 ns and on-chip address latches. Symp. on VLSI Technology Techn. Dig. (1984) pp.52–53

    Google Scholar 

  24. K. Yamguchi, H. Nambu, K. Kanetani, N. Homma, Y. Nishioka, A. Uchida, K. Ogiue: A 3.5ns, 2W, 20mm2 16kb ECL bipolar RAM. ISSCC Techn. Dig. (1986) pp.214–215

    Google Scholar 

  25. M. Arimura, M. Nakamae, T. Tashiro, S. Ohi, T. Kamiya, S. Kishi, Y. Minato, J. Nokubo, T. Tamura: A 4ns access time 4kx4 ECL RAM. ISSCC Techn. Dig. (1986) pp.254–255

    Google Scholar 

  26. M. Suzuki, M. Hirata, T. Itoh: A 165ps/gate 5000-gate ECL gate array. CSSDM (Tokyo) Techn. Dig. (1985) pp.377–380

    Google Scholar 

  27. Y.H. Chan, J.L. Brown, R.H. Nijhuis, C.R. Rivadeneira, J.R. Struk: A 3 ns 32k bipolar RAM. ISSCC Techn. Dig. (1986) pp.210–211

    Google Scholar 

  28. C.T. Chuang, D.D. Tang, G.P. Li, R.L. Franch, M.B. Ketchen, T.H. Ning, K.H. Brown, C.C. Hu: A sub-nanosecond 5 kbit bipolar ECL RAM. Symp. on VLSI Technology, Techn. Dig. (1988) pp.91–92

    Google Scholar 

  29. F. Buckley, S.Y. Chen, J.K. Hilse, M.E. Homan, G.K. Machol. L. Pereira, J. Terry, G.T. Watanabe: A bipolar 32b processor chip. ISSCC Techn. Dig. (1986) pp.30–31

    Google Scholar 

  30. P. Thai, S.C. Chang, M.C. Yang: A 35ns 128k fusible bipolar PROM. ISSCC Techn. Dig. (1986) pp.44–45

    Google Scholar 

  31. D. Chang, C. Schmitz, H. Hingarh, G. Bakker: A 0.9ns ECL 16x4 register file. ISSCC Techn. Dig. (1986) pp. 188–189

    Google Scholar 

  32. E.H. Stevens, W.L. Larson, J.A. Kiddon, B.D. Urke: A bipolar technology for ULSI applications. VLSI Design 6, 92–99 (January 1985)

    Google Scholar 

  33. A. Matsuzawa, A. Kanda, M. Kagawa, H. Yamada: An 200Msps 8-bit A/D converter with a duplex gray coding. Symp. on VLSI Circuit, Techn. Dig. (1987) pp.109–110

    Google Scholar 

  34. A bipolar process that’s repelling CMOS. Electronics 58, 45-47 (Dec. 23, 1985)

    Google Scholar 

  35. TI’s answer to the need for faster VLSI: its ExCL process. Electronics 60, 73-75 (March 19, 1987)

    Google Scholar 

  36. K. Sagara, Y. Tamaki, M. Kawamura: Evaluation of dislocation generation in silicon substrates by selective oxidation of U-grooves. J. Electrochem. Soc. 134, 500–502 (1987)

    Article  CAS  Google Scholar 

  37. Y. Tamaki, S. Isomae, K. Sagara, T. Kure, M. Kawamura: Evaluation of dislocation generation in U-groove isolation. J. Electrochem. Soc. 35, 726–730 (1988)

    Article  Google Scholar 

  38. C.W. Teng, C. Slawinski, W.R. Hunter: Defect generation in trench isolation. IEDM Techn. Dig. (1984) pp.586–589

    Google Scholar 

  39. K. Hashimoto, Y. Nagakubo, S. Yokogawa, M. Kakumu, M. Kinugawa, K. Sawada, T. Sakurai, M. Isobe, J. Matsunaga, T. Iizuka: Deep trench well isolation for 256kb 6T CMOS static RAM. Symp. on VLSI Technology, Techn. Dig. (1985) pp.94–95

    Google Scholar 

  40. J. Riseman: Integrated circuit structure with fully enclosed air isolation. U.S. Patent 4106050 (August 1978)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1988 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Goto, H., Inayoshi, K. (1988). Trench Isolation Schemes for Bipolar Devices: Benefits and Limiting Aspects. In: Treitinger, L., Miura-Mattausch, M. (eds) Ultra-Fast Silicon Bipolar Technology. Springer Series in Electronics and Photonics, vol 27. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-74360-3_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-74360-3_4

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-74362-7

  • Online ISBN: 978-3-642-74360-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics