Skip to main content
SpringerLink
Log in
Book cover

Parallelrechner-Architekturen pp 1–17Cite as

Einleitung

  • Chapter

  • 27 Accesses

Zusammenfassung

Der Bedarf nach mehr Leistung, also höherer Verarbeitungsgeschwindigkeit der Rechenanlagen einerseits, und die physikalisch-technischen Grenzen der Bauelemente andererseits, bilden die Grundlage für den Wunsch nach Parallelverarbeitung. Bisherige Veröffentlichungen und Studien befassen sich ausführlich mit der Hardwareseite von Parallelrechnern und heutigen Supercomputern [Hwa84], [Joh86], [Kle87]. Wechselwirkungen zwischen Technologie und Rechnerarchitektur werden in [Kob86] erläutert.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   54.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   69.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Literaturverzeichnis

  1. Altenkrüger, D.E.: Sprachparadigmen im Wandel, in: Schwärtzel, H. (Hrsg.): Informatik in der Praxis, Berlin, Heidelberg, New York, Tokyo: Springer 1986, 281–292

    Google Scholar 

  2. Amamiya, M.; et al.: A List-processing-oriented Data Flow Machine Architecture, in: AFIPS Conf. Proc. NCC 1982, 143–151

    Google Scholar 

  3. Beneš, V.E.: Mathematical Theorie of Connecting Networks and Telephon Traffic, New York: Academip Press 1964

    Google Scholar 

  4. Bhuyan, L.N.; Agrawal, D.P.: Design and Performance of Generalized Interconnection Networks, IEEE Transactions on Computers, C-32 (1983), 1081–1090

    Article  Google Scholar 

  5. Bishop, P.B.: Computer Systems with a very Large Adress Space and Garbage Collection, Techn. Report TR-178, Laboratory for Computer Science, Cambridge, Mass., 1977

    Google Scholar 

  6. Cheney, J.: Nonrecursive List Compacting Algorithm, CACM 13 (1970), 677–678

    MATH  Google Scholar 

  7. Clark, D.W.; Green, C.C.: An Empirical Study of List Structure in Lisp, CACM 20 (1977), 78–86

    MATH  Google Scholar 

  8. Clos, C.: A Study on NonBlocking Switching Networks, Bell Systems Technical Journal 32 (1953), 406–424

    Google Scholar 

  9. Cohen, J.: Garbage Collection of Linked Data Structures, Computing Surveys 13 (1981), 341–367

    Article  MathSciNet  Google Scholar 

  10. Collins, G.E.: A Method for Overlapping and Erasure of Lists, CACM 3 (1960), 655–657

    Google Scholar 

  11. Deutsch, L.; Bobrow, D.: An Effizient, Incremental, Automatic Garbage Collector, CACM 19 (1976), 522–526

    MATH  Google Scholar 

  12. Eisenbach, S.: Declarative Languages: An Overview, Byte, Nr. 8, 1985, 181–197

    Google Scholar 

  13. Fenichel, R.; Yochelson, J.: A LISP Garbage Collector for Virtual Memory Computer Systems, CACM 12(1969), 611–612

    MATH  Google Scholar 

  14. Giloi, W. K.: Rechnerarchitektur, Berlin, Heidelberg, New York, Tokyo: Springer 1981

    MATH  Google Scholar 

  15. Hillis, W.D.: The Connection Machine, Cambridge, Mass.: The MIT Press 1985

    Google Scholar 

  16. Hwang, K.; Briggs, F.A.: Computer Architecture and Parallel Processing, New York: McGraw-Hill 1984

    MATH  Google Scholar 

  17. Johnson, T.; Durham, T.: Parallel Processing: the challenge of new computer architectures, London, Princeton, N.J.: Ovum 1986

    Google Scholar 

  18. Klein, A.; Eckardt, H.; Istavrinos, P.: Parallelrechner Architekturen, eine Studie zum Stand der Technik, Siemens AG, Bericht, Aktz. ZT ZTI SYS 1–52 Kl/Eck/I/Wi, 1987

    Google Scholar 

  19. Kober, R.; Müller-Schloer, Ch.; Schmitter, E.: Chancen für Parallelarchitekturen, in Schwärtzel, H. (Hrsg.): Informatik in der Praxis, Berlin, Heidelberg, New York, Tokyo: Springer 1986, 295–313

    Google Scholar 

  20. Lee, M.; Wu, C-L.: Performance Analysis of Circuit Switching Baseline Interconnection Networks, in: Proc. 11th Symposium on Computer Architecture, 1984, 82–90

    Google Scholar 

  21. Lieberman, H.; Hewitt, C.: A Real Time Garbage Collector that can Recover Temporary Storage Quickly, Technical Report 569, Artificial Intelligence Laboratory, MIT, 1980

    Google Scholar 

  22. Matsuda, H.; Kokata, M.; Masuo, T.; Kaneda, Y.; Maekawa, S.: Parallel Prolog Machine PARK: Its Hardware Structure and Prolog System, in: Proc. 4th Conference on Logic Programming ’85, 1985

    Google Scholar 

  23. Oxley, D. W.: European Patent Application, Publ. No. 0 173 464 A2, 1986

    Google Scholar 

  24. Patel, J.H.: Performance of Processor-Memory Interconnections for Multiprocessors, IEEE Transactions on Computers, C-30 (1981), 771–780

    Article  Google Scholar 

  25. Regenspurg, G.: Hochleistungsrechner - Architekturprinzipien, Hamburg: Mc Graw-Hill 1987

    Google Scholar 

  26. Sohma, Y.; Satoh, K.; Kumon, K.; Masuzawa, H.; Itashiki, A.: A New Parallel Inference Mechanism based on Sequential Processing, in: Proc. IFIP TC-10 Working Conf. on Fifth Generation Computer Architecture, 1985, 3–14

    Google Scholar 

  27. Siegel, H.J.: Interconnection Networks for Large Scale Parallel Processing, Lexington Mass.: Lexington Books 1985

    Google Scholar 

  28. Umeyama, S.; Tamura, K.: A Parallel Execution Model of Logic Programs, in: Proc. 10th Annual Int. Conf. on Computer Architecture, 1983, 349–355

    Google Scholar 

  29. Ungar, D. : Generation Scavenging: A Non-disruptive High Performance-Storage Reclamation Algorithm, in: Proc. ACM SIGSOFT/SIGPLAN Software Engineering Symposium on Practical Software Development Environments, 1984, 157–167

    Chapter  Google Scholar 

  30. Waltz, D.L.: Application of the Connection Machine, Computer, Nr. 1, 1987, 85–97

    Google Scholar 

  31. Woo, N.S.: A Hardware Unification Unit: Design and Analysis, in: Proc. 12th Annual Int. Symposium on Computer Architecture, 1985, 198–205

    Google Scholar 

  32. Wu, C.; Feng, T.: On a Class of Multistage Interconnection Networks, IEEE Transactions on Computers C-29 (1980), 694–702

    Article  MathSciNet  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Siemens AG, München, Germany

    Rudolf Kober Dipl.-Ing. (Leiter der Abteilung Prozessorarchitektur im Hauptbereich Zentrale Aufgaben Informationstechnik)

Authors
  1. Rudolf Kober Dipl.-Ing.
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Siemens AG, München, Germany

    Rudolf Kober (Leiter der Abteilung Prozessorarchitektur im Hauptbereich Zentrale Aufgaben Informationstechnik) (Leiter der Abteilung Prozessorarchitektur im Hauptbereich Zentrale Aufgaben Informationstechnik)

Rights and permissions

Reprints and permissions

Copyright information

© 1988 Springer-Verlag Berlin, Heidelberg

About this chapter

Cite this chapter

Kober, R. (1988). Einleitung. In: Kober, R. (eds) Parallelrechner-Architekturen. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-73896-8_1

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-73896-8_1

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-50038-4

  • Online ISBN: 978-3-642-73896-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation